Commit e909abe8 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'coresight-next-v6.8' of... 

Merge tag 'coresight-next-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux

 into char-misc-next

Suzuki writes:

coresight: Updates for Linux v6.8

Updates for the hwtracing subsystem includes :
 - Support for CoreSight TPDM DSB set
 - Support for tuning Cycle count Threshold for CoreSight ETM via perf
 - Support for TRBE on ACPI based systems
 - Support for choosing buffer mode in ETR for sysfs mode
 - Improvements to HiSilicon PTT driver
 - Cleanups to Ultrasoc SMB driver
 - Cleanup .remove callback for various Coresight platform drivers
 - Remove Leo Yan from Reviewers

Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>

* tag 'coresight-next-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux: (32 commits)
  coresight: ultrasoc-smb: Use guards to cleanup
  coresight: ultrasoc-smb: Convert to platform remove callback returning void
  coresight: trbe: Convert to platform remove callback returning void
  coresight: replicator: Convert to platform remove callback returning void
  coresight: funnel: Convert to platform remove callback returning void
  coresight: etm4x: Convert to platform remove callback returning void
  coresight: dummy: Convert to platform remove callback returning void
  coresight: etm4x: Fix width of CCITMIN field
  coresight-tpdm: Correct the property name of MSR number
  hwtracing: hisi_ptt: Optimize the trace data committing
  hwtracing: hisi_ptt: Disable interrupt after trace end
  Documentation: ABI: coresight-tpdm: Fix Bit[3] description indentation
  coresight-tpdm: Add nodes for dsb msr support
  dt-bindings: arm: Add support for DSB MSR register
  coresight-tpdm: Add nodes for timestamp request
  coresight-tpdm: Add nodes to configure pattern match output
  coresight-tpdm: Add nodes for dsb edge control
  coresight-tpdm: Add node to set dsb programming mode
  coresight-tpdm: Add nodes to set trigger timestamp and type
  coresight-tpdm: Add reset node to TPDM node
  ...
parents 0e42b5fe 60e5f23d

Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc

+16 −0
Original line number Diff line number Diff line
@@ -91,3 +91,19 @@ Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 
Description:	(RW) Size of the trace buffer for TMC-ETR when used in SYSFS

		mode. Writable only for TMC-ETR configurations. The value

		should be aligned to the kernel pagesize.



What:		/sys/bus/coresight/devices/<memory_map>.tmc/buf_modes_available

Date:		August 2023

KernelVersion:	6.7

Contact:	Anshuman Khandual <anshuman.khandual@arm.com>

Description:	(Read) Shows all supported Coresight TMC-ETR buffer modes available

		for the users to configure explicitly. This file is avaialble only

		for TMC ETR devices.



What:		/sys/bus/coresight/devices/<memory_map>.tmc/buf_mode_preferred

Date:		August 2023

KernelVersion:	6.7

Contact:	Anshuman Khandual <anshuman.khandual@arm.com>

Description:	(RW) Current Coresight TMC-ETR buffer mode selected. But user could

		only provide a mode which is supported for a given ETR device. This

		file is available only for TMC ETR devices.

Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm

+159 −0
Original line number Diff line number Diff line
@@ -11,3 +11,162 @@ Description: 
		Accepts only one of the 2 values -  1 or 2.

		1 : Generate 64 bits data

		2 : Generate 32 bits data



What:		/sys/bus/coresight/devices/<tpdm-name>/reset_dataset

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(Write) Reset the dataset of the tpdm.



		Accepts only one value -  1.

		1 : Reset the dataset of the tpdm



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get the trigger type of the DSB for tpdm.



		Accepts only one of the 2 values -  0 or 1.

		0 : Set the DSB trigger type to false

		1 : Set the DSB trigger type to true



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get the trigger timestamp of the DSB for tpdm.



		Accepts only one of the 2 values -  0 or 1.

		0 : Set the DSB trigger type to false

		1 : Set the DSB trigger type to true



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_mode

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get the programming mode of the DSB for tpdm.



		Accepts the value needs to be greater than 0. What data

		bits do is listed below.

		Bit[0:1] : Test mode control bit for choosing the inputs.

		Bit[3] : Set to 0 for low performance mode. Set to 1 for high

		performance mode.

		Bit[4:8] : Select byte lane for high performance mode.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get the index number of the edge detection for the DSB

		subunit TPDM. Since there are at most 256 edge detections, this

		value ranges from 0 to 255.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		Write a data to control the edge detection corresponding to

		the index number. Before writing data to this sysfs file,

		"ctrl_idx" should be written first to configure the index

		number of the edge detection which needs to be controlled.



		Accepts only one of the following values.

		0 - Rising edge detection

		1 - Falling edge detection

		2 - Rising and falling edge detection (toggle detection)





What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		Write a data to mask the edge detection corresponding to the index

		number. Before writing data to this sysfs file, "ctrl_idx" should

		be written first to configure the index number of the edge detection

		which needs to be masked.



		Accepts only one of the 2 values -  0 or 1.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		Read a set of the edge control value of the DSB in TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		Read a set of the edge control mask of the DSB in TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get the value of the trigger pattern for the DSB

		subunit TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get the mask of the trigger pattern for the DSB

		subunit TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get the value of the pattern for the DSB subunit TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get the mask of the pattern for the DSB subunit TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(Write) Set the pattern timestamp of DSB tpdm. Read

		the pattern timestamp of DSB tpdm.



		Accepts only one of the 2 values -  0 or 1.

		0 : Disable DSB pattern timestamp.

		1 : Enable DSB pattern timestamp.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(Write) Set the pattern type of DSB tpdm. Read

		the pattern type of DSB tpdm.



		Accepts only one of the 2 values -  0 or 1.

		0 : Set the DSB pattern type to value.

		1 : Set the DSB pattern type to toggle.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]

Date:		March 2023

KernelVersion	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Description:

		(RW) Set/Get the MSR(mux select register) for the DSB subunit

		TPDM.

Documentation/arch/arm64/silicon-errata.rst

+10 −0
Original line number Diff line number Diff line
@@ -117,6 +117,10 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1490853        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1491015        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |
@@ -127,6 +131,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A715     | #2645198        | ARM64_ERRATUM_2645198       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X1       | #1502854        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |
@@ -135,6 +141,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1490853        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1542419        | ARM64_ERRATUM_1542419       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2139208        | ARM64_ERRATUM_2139208       |
@@ -143,6 +151,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V1     | #1619801        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-600         | #1076982,1209401| N/A                         |

Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml

+20 −0
Original line number Diff line number Diff line
@@ -44,6 +44,23 @@ properties: 
    minItems: 1

    maxItems: 2



  qcom,dsb-element-size:

    description:

      Specifies the DSB(Discrete Single Bit) element size supported by

      the monitor. The associated aggregator will read this size before it

      is enabled. DSB element size currently only supports 32-bit and 64-bit.

    $ref: /schemas/types.yaml#/definitions/uint8

    enum: [32, 64]



  qcom,dsb-msrs-num:

    description:

      Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)

      registers supported by the monitor. If this property is not configured

      or set to 0, it means this DSB TPDM doesn't support MSR.

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 0

    maximum: 32



  clocks:

    maxItems: 1
@@ -77,6 +94,9 @@ examples: 
      compatible = "qcom,coresight-tpdm", "arm,primecell";

      reg = <0x0684c000 0x1000>;



      qcom,dsb-element-size = /bits/ 8 <32>;

      qcom,dsb-msrs-num = <16>;



      clocks = <&aoss_qmp>;

      clock-names = "apb_pclk";

Documentation/trace/coresight/coresight.rst

+4 −0
Original line number Diff line number Diff line
@@ -624,6 +624,10 @@ They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/ 
   * - timestamp

     - Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP

       <coresight-timestamp>`

   * - cc_threshold

     - Cycle count threshold value. If nothing is provided here or the provided value is 0, then the

       default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold

       value, as indicated via TRCIDR3.CCITMIN, then the minimum value will be used instead.



How to use the STM module

-------------------------