Unverified Commit e913aec7 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno
Browse files

arm64: dts: mediatek: mt8395-nio-12l: Preconfigure DSI0 pipeline 

This board can use a MIPI-DSI panel on the DSI0 connector: in
preparation for adding an overlay for the Radxa Display 8HD,
add a pipeline connecting VDOSYS0 components to DSI0.

This pipeline remains disabled by default, as it is expected
to be enabled only by a devicetree overlay that declares the
actual DSI panel node, completing the graph.

Link: https://lore.kernel.org/r/20250213112008.56394-4-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent df514c11

arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts

+26 −0
Original line number Diff line number Diff line
@@ -172,6 +172,32 @@ &cpu7 { 
	cpu-supply = <&mt6315_6_vbuck1>;

};



&dither0_out {

	remote-endpoint = <&dsi0_in>;

};



&dsi0 {

	#address-cells = <1>;

	#size-cells = <0>;



	ports {

		#address-cells = <1>;

		#size-cells = <0>;



		port@0 {

			reg = <0>;

			dsi0_in: endpoint {

				remote-endpoint = <&dither0_out>;

			};

		};



		port@1 {

			reg = <1>;

			dsi0_out: endpoint { };

		};

	};

};



&eth {

	phy-mode = "rgmii-rxid";

	phy-handle = <&rgmii_phy>;