Commit e93eee52 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: don't select single flush for active CTL blocks 



In case of ACTIVE CTLs, a single CTL is being used for flushing all INTF
blocks. Don't skip programming the CTL on those targets.

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/641585/
Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-5-5d20655f10ca@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent df99bdfc

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

+2 −1
Original line number Diff line number Diff line
@@ -374,7 +374,8 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg) 
static bool dpu_encoder_phys_vid_needs_single_flush(

		struct dpu_encoder_phys *phys_enc)

{

	return phys_enc->split_role != ENC_ROLE_SOLO;

	return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) &&

		phys_enc->split_role != ENC_ROLE_SOLO;

}



static void dpu_encoder_phys_vid_atomic_mode_set(