Commit e94b45d0 authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Jens Axboe
Browse files

block: move dma_pad_mask into queue_limits 



dma_pad_mask is a queue_limits by all ways of looking at it, so move it
there and set it through the atomic queue limits APIs.

Add a little helper that takes the alignment and pad into account to
simplify the code that is touched a bit.

Note that there never was any need for the > check in
blk_queue_update_dma_pad, this probably was just copy and paste from
dma_update_dma_alignment.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Reviewed-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Link: https://lore.kernel.org/r/20240626142637.300624-9-hch@lst.de


Signed-off-by: default avatarJens Axboe <axboe@kernel.dk>
parent abfc9d81

block/bio-integrity.c

+1 −1
Original line number Diff line number Diff line
@@ -312,7 +312,7 @@ int bio_integrity_map_user(struct bio *bio, void __user *ubuf, ssize_t bytes, 
			   u32 seed)

{

	struct request_queue *q = bdev_get_queue(bio->bi_bdev);

	unsigned int align = q->dma_pad_mask | queue_dma_alignment(q);

	unsigned int align = blk_lim_dma_alignment_and_pad(&q->limits);

	struct page *stack_pages[UIO_FASTIOV], **pages = stack_pages;

	struct bio_vec stack_vec[UIO_FASTIOV], *bvec = stack_vec;

	unsigned int direction, nr_bvecs;

block/blk-map.c

+1 −1
Original line number Diff line number Diff line
@@ -634,7 +634,7 @@ int blk_rq_map_user_iov(struct request_queue *q, struct request *rq, 
			const struct iov_iter *iter, gfp_t gfp_mask)

{

	bool copy = false, map_bvec = false;

	unsigned long align = q->dma_pad_mask | queue_dma_alignment(q);

	unsigned long align = blk_lim_dma_alignment_and_pad(&q->limits);

	struct bio *bio = NULL;

	struct iov_iter i;

	int ret = -EINVAL;

block/blk-settings.c

+0 −17
Original line number Diff line number Diff line
@@ -768,23 +768,6 @@ bool queue_limits_stack_integrity(struct queue_limits *t, 
}

EXPORT_SYMBOL_GPL(queue_limits_stack_integrity);



/**

 * blk_queue_update_dma_pad - update pad mask

 * @q:     the request queue for the device

 * @mask:  pad mask

 *

 * Update dma pad mask.

 *

 * Appending pad buffer to a request modifies the last entry of a

 * scatter list such that it includes the pad buffer.

 **/

void blk_queue_update_dma_pad(struct request_queue *q, unsigned int mask)

{

	if (mask > q->dma_pad_mask)

		q->dma_pad_mask = mask;

}

EXPORT_SYMBOL(blk_queue_update_dma_pad);



/**

 * blk_set_queue_depth - tell the block layer about the device queue depth

 * @q:		the request queue for the device

drivers/ata/libata-scsi.c

+1 −2
Original line number Diff line number Diff line
@@ -1024,7 +1024,6 @@ EXPORT_SYMBOL_GPL(ata_scsi_dma_need_drain); 
int ata_scsi_dev_config(struct scsi_device *sdev, struct queue_limits *lim,

		struct ata_device *dev)

{

	struct request_queue *q = sdev->request_queue;

	int depth = 1;



	if (!ata_id_has_unload(dev->id))
@@ -1038,7 +1037,7 @@ int ata_scsi_dev_config(struct scsi_device *sdev, struct queue_limits *lim, 
		sdev->sector_size = ATA_SECT_SIZE;



		/* set DMA padding */

		blk_queue_update_dma_pad(q, ATA_DMA_PAD_SZ - 1);

		lim->dma_pad_mask = ATA_DMA_PAD_SZ - 1;



		/* make room for appending the drain */

		lim->max_segments--;

drivers/ata/pata_macio.c

+2 −2
Original line number Diff line number Diff line
@@ -816,7 +816,7 @@ static int pata_macio_device_configure(struct scsi_device *sdev, 
	/* OHare has issues with non cache aligned DMA on some chipsets */

	if (priv->kind == controller_ohare) {

		lim->dma_alignment = 31;

		blk_queue_update_dma_pad(sdev->request_queue, 31);

		lim->dma_pad_mask = 31;



		/* Tell the world about it */

		ata_dev_info(dev, "OHare alignment limits applied\n");
@@ -831,7 +831,7 @@ static int pata_macio_device_configure(struct scsi_device *sdev, 
	if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {

		/* Allright these are bad, apply restrictions */

		lim->dma_alignment = 15;

		blk_queue_update_dma_pad(sdev->request_queue, 15);

		lim->dma_pad_mask = 15;



		/* We enable MWI and hack cache line size directly here, this

		 * is specific to this chipset and not normal values, we happen