Commit e955b547 authored by Ilya Bakoulin's avatar Ilya Bakoulin Committed by Alex Deucher
Browse files

drm/amd/display: Add Audio readback registers 



[Why]
Can be useful for verifying the correctness of audio output.

Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarIlya Bakoulin <Ilya.Bakoulin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 89c342a9

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#include <linux/delay.h>



#include "dm_services.h"

#include "dc_bios_types.h"

#include "dcn10_stream_encoder.h"

#include "reg_helper.h"

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

+8 −0
Original line number Diff line number Diff line
@@ -92,6 +92,8 @@ 
	SRI(DP_VID_STREAM_CNTL, DP, id), \

	SRI(DP_VID_TIMING, DP, id), \

	SRI(DP_SEC_AUD_N, DP, id), \

	SRI(DP_SEC_AUD_N_READBACK, DP, id), \

	SRI(DP_SEC_AUD_M_READBACK, DP, id), \

	SRI(DP_SEC_TIMESTAMP, DP, id), \

	SRI(DIG_CLOCK_PATTERN, DIG, id)
@@ -140,6 +142,8 @@ struct dcn10_stream_enc_registers { 
	uint32_t DP_VID_STREAM_CNTL;

	uint32_t DP_VID_TIMING;

	uint32_t DP_SEC_AUD_N;

	uint32_t DP_SEC_AUD_N_READBACK;

	uint32_t DP_SEC_AUD_M_READBACK;

	uint32_t DP_SEC_TIMESTAMP;

	uint32_t HDMI_CONTROL;

	uint32_t HDMI_GC;
@@ -256,6 +260,8 @@ struct dcn10_stream_enc_registers { 
	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\

	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\

	SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\

	SE_SF(DP0_DP_SEC_AUD_N_READBACK, DP_SEC_AUD_N_READBACK, mask_sh),\

	SE_SF(DP0_DP_SEC_AUD_M_READBACK, DP_SEC_AUD_M_READBACK, mask_sh),\

	SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\

	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\

	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
@@ -473,6 +479,8 @@ struct dcn10_stream_enc_registers { 
	type AFMT_60958_CS_CHANNEL_NUMBER_6;\

	type AFMT_60958_CS_CHANNEL_NUMBER_7;\

	type DP_SEC_AUD_N;\

	type DP_SEC_AUD_N_READBACK;\

	type DP_SEC_AUD_M_READBACK;\

	type DP_SEC_TIMESTAMP_MODE;\

	type DP_SEC_ASP_ENABLE;\

	type DP_SEC_ATP_ENABLE;\

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h

+4 −0
Original line number Diff line number Diff line
@@ -95,6 +95,8 @@ 
	SRI(DP_VID_STREAM_CNTL, DP, id), \

	SRI(DP_VID_TIMING, DP, id), \

	SRI(DP_SEC_AUD_N, DP, id), \

	SRI(DP_SEC_AUD_N_READBACK, DP, id), \

	SRI(DP_SEC_AUD_M_READBACK, DP, id), \

	SRI(DP_SEC_TIMESTAMP, DP, id), \

	SRI(DP_DSC_CNTL, DP, id), \

	SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
@@ -157,6 +159,8 @@ 
	SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\

	SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\

	SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\

	SE_SF(DP0_DP_SEC_AUD_N_READBACK, DP_SEC_AUD_N_READBACK, mask_sh),\

	SE_SF(DP0_DP_SEC_AUD_M_READBACK, DP_SEC_AUD_M_READBACK, mask_sh),\

	SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\

	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\

	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\