Commit e9621ef6 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: Fix a7xx TPL1 cluster snapshot 



Later gens have both a PIPE_BR and PIPE_NONE section.  The snapshot tool
seems to expect this for x1-85 as well.  I guess this was just a bug in
downstream kgsl, which went unnoticed?

Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/666662/
parent a814ba2d

drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h

+9 −2
Original line number Diff line number Diff line
@@ -668,12 +668,19 @@ static const u32 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers[] = { 
};

static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers), 8));



/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */

static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = {

/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_NONE */

static const u32 gen7_0_0_tpl1_noncontext_pipe_none_registers[] = {

	0x0b600, 0x0b600, 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c,

	0x0b60f, 0x0b621, 0x0b630, 0x0b633,

	UINT_MAX, UINT_MAX,

};

static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_none_registers), 8));



/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */

static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = {

	 0x0b600, 0x0b600,

	 UINT_MAX, UINT_MAX,

};

static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_br_registers), 8));



/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_LPAC */

drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h

+2 −0
Original line number Diff line number Diff line
@@ -573,6 +573,8 @@ static const struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = { 
		gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 },

	{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,

		gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 },

	{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_NONE, 0, A7XX_USPTP,

		gen7_0_0_tpl1_noncontext_pipe_none_registers, 0xb600 },

	{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,

		gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 },

	{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,