Commit e96b0420 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.11-tag2' of... 

Merge tag 'renesas-clk-for-v6.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Remove obsolete clock DT binding header files
 - Add Battery Backup (VBATTB) and I2C clocks, resets, and power
   domains on RZ/G3S
 - Add audio clocks on R-Car V4M
 - Add video capture (ISPCS, CSI-2, VIN) clocks on R-Car V4M
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C
  clk: renesas: r8a779h0: Add Audio clocks
  clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP
  dt-bindings: clock: rcar-gen2: Remove obsolete header files
  dt-bindings: clock: r8a7779: Remove duplicate newline
  clk: renesas: Drop "Renesas" from individual driver descriptions
  clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments
  clk: renesas: r8a779h0: Add VIN clocks
  dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells
  clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock
  clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock
  clk: renesas: r8a77970: Use common cpg_lock
  clk: renesas: r8a779h0: Add CSI-2 clocks
  clk: renesas: r8a779h0: Add ISPCS clocks
parents 1613e604 c7e58843

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ properties: 


  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      The single reset specifier cell must be the reset number, as defined in

      <dt-bindings/clock/r9a0*-cpg.h>.

    const: 1

drivers/clk/renesas/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -218,14 +218,14 @@ config CLK_RCAR_GEN4_CPG 
	select CLK_RENESAS_CPG_MSSR



config CLK_RCAR_USB2_CLOCK_SEL

	bool "Renesas R-Car USB2 clock selector support"

	bool "R-Car USB2 clock selector support"

	depends on ARCH_RENESAS || COMPILE_TEST

	select RESET_CONTROLLER

	help

	  This is a driver for R-Car USB2 clock selector



config CLK_RZG2L

	bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST

	bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST

	select RESET_CONTROLLER



# Generic

drivers/clk/renesas/r8a77970-cpg-mssr.c

+1 −4
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>



#include "renesas-cpg-mssr.h"

#include "rcar-cpg-lib.h"

#include "rcar-gen3-cpg.h"



#define CPG_SD0CKCR		0x0074
@@ -47,8 +48,6 @@ enum clk_ids { 
	MOD_CLK_BASE

};



static spinlock_t cpg_lock;



static const struct clk_div_table cpg_sd0h_div_table[] = {

	{  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },

	{  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
@@ -213,8 +212,6 @@ static int __init r8a77970_cpg_mssr_init(struct device *dev) 
	if (error)

		return error;



	spin_lock_init(&cpg_lock);



	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];



	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);

drivers/clk/renesas/r8a779h0-cpg-mssr.c

+25 −3
Original line number Diff line number Diff line
@@ -176,6 +176,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { 
	DEF_MOD("avb0:rgmii0",	211,	R8A779H0_CLK_S0D8_HSC),

	DEF_MOD("avb1:rgmii1",	212,	R8A779H0_CLK_S0D8_HSC),

	DEF_MOD("avb2:rgmii2",	213,	R8A779H0_CLK_S0D8_HSC),

	DEF_MOD("csi40",	331,	R8A779H0_CLK_CSI),

	DEF_MOD("csi41",	400,	R8A779H0_CLK_CSI),

	DEF_MOD("hscif0",	514,	R8A779H0_CLK_SASYNCPERD1),

	DEF_MOD("hscif1",	515,	R8A779H0_CLK_SASYNCPERD1),

	DEF_MOD("hscif2",	516,	R8A779H0_CLK_SASYNCPERD1),
@@ -185,6 +187,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { 
	DEF_MOD("i2c2",		520,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("i2c3",		521,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("irqc",		611,	R8A779H0_CLK_CL16M),

	DEF_MOD("ispcs0",	612,	R8A779H0_CLK_S0D2_VIO),

	DEF_MOD("ispcs1",	613,	R8A779H0_CLK_S0D2_VIO),

	DEF_MOD("msi0",		618,	R8A779H0_CLK_MSO),

	DEF_MOD("msi1",		619,	R8A779H0_CLK_MSO),

	DEF_MOD("msi2",		620,	R8A779H0_CLK_MSO),
@@ -204,6 +208,22 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { 
	DEF_MOD("tmu2",		715,	R8A779H0_CLK_SASYNCPERD2),

	DEF_MOD("tmu3",		716,	R8A779H0_CLK_SASYNCPERD2),

	DEF_MOD("tmu4",		717,	R8A779H0_CLK_SASYNCPERD2),

	DEF_MOD("vin00",	730,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin01",	731,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin02",	800,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin03",	801,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin04",	802,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin05",	803,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin06",	804,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin07",	805,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin10",	806,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin11",	807,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin12",	808,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin13",	809,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin14",	810,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin15",	811,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin16",	812,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("vin17",	813,	R8A779H0_CLK_S0D4_VIO),

	DEF_MOD("wdt1:wdt0",	907,	R8A779H0_CLK_R),

	DEF_MOD("cmt0",		910,	R8A779H0_CLK_R),

	DEF_MOD("cmt1",		911,	R8A779H0_CLK_R),
@@ -213,6 +233,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { 
	DEF_MOD("pfc1",		916,	R8A779H0_CLK_CP),

	DEF_MOD("pfc2",		917,	R8A779H0_CLK_CP),

	DEF_MOD("tsc2:tsc1",	919,	R8A779H0_CLK_CL16M),

	DEF_MOD("ssiu",		2926,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("ssi",		2927,	R8A779H0_CLK_S0D6_PER),

};



/*
@@ -222,10 +244,10 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { 
 *   MD	 EXTAL		PLL1	PLL2	PLL3	PLL4	PLL5	PLL6	OSC

 * 14 13 (MHz)

 * ------------------------------------------------------------------------

 * 0  0	 16.66 / 1	x192	x204	x192	x144	x192	x168	/16

 * 0  1	 20    / 1	x160	x170	x160	x120	x160	x140	/19

 * 0  0	 16.66 / 1	x192	x240	x192	x240	x192	x168	/16

 * 0  1	 20    / 1	x160	x200	x160	x200	x160	x140	/19

 * 1  0	 Prohibited setting

 * 1  1	 33.33 / 2	x192	x204	x192	x144	x192	x168	/32

 * 1  1	 33.33 / 2	x192	x240	x192	x240	x192	x168	/32

 */

#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \

					 (((md) & BIT(13)) >> 13))

drivers/clk/renesas/r9a08g045-cpg.c

+26 −0
Original line number Diff line number Diff line
@@ -213,8 +213,13 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { 
	DEF_COUPLED("eth1_axi",		R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),

	DEF_COUPLED("eth1_chi",		R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),

	DEF_MOD("eth1_refclk",		R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),

	DEF_MOD("i2c0_pclk",		R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0),

	DEF_MOD("i2c1_pclk",		R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1),

	DEF_MOD("i2c2_pclk",		R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),

	DEF_MOD("i2c3_pclk",		R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),

	DEF_MOD("scif0_clk_pck",	R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),

	DEF_MOD("gpio_hclk",		R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),

	DEF_MOD("vbat_bclk",		R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),

};



static const struct rzg2l_reset r9a08g045_resets[] = {
@@ -227,10 +232,15 @@ static const struct rzg2l_reset r9a08g045_resets[] = { 
	DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),

	DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),

	DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),

	DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0),

	DEF_RST(R9A08G045_I2C1_MRST, 0x880, 1),

	DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),

	DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),

	DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),

	DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),

	DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),

	DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),

	DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),

};



static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
@@ -238,6 +248,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { 
	MOD_CLK_BASE + R9A08G045_IA55_PCLK,

	MOD_CLK_BASE + R9A08G045_IA55_CLK,

	MOD_CLK_BASE + R9A08G045_DMAC_ACLK,

	MOD_CLK_BASE + R9A08G045_VBAT_BCLK,

};



static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
@@ -272,9 +283,24 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { 
	DEF_PD("eth1",		R9A08G045_PD_ETHER1,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),

				RZG2L_PD_F_NONE),

	DEF_PD("i2c0",		R9A08G045_PD_I2C0,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)),

				RZG2L_PD_F_NONE),

	DEF_PD("i2c1",		R9A08G045_PD_I2C1,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)),

				RZG2L_PD_F_NONE),

	DEF_PD("i2c2",		R9A08G045_PD_I2C2,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)),

				RZG2L_PD_F_NONE),

	DEF_PD("i2c3",		R9A08G045_PD_I2C3,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)),

				RZG2L_PD_F_NONE),

	DEF_PD("scif0",		R9A08G045_PD_SCIF0,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),

				RZG2L_PD_F_NONE),

	DEF_PD("vbat",		R9A08G045_PD_VBAT,

				DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),

				RZG2L_PD_F_ALWAYS_ON),

};



const struct rzg2l_cpg_info r9a08g045_cpg_info = {