Commit e980aa68 authored by Karol Kolacinski's avatar Karol Kolacinski Committed by Tony Nguyen
Browse files

ice: move TSPLL init calls to ice_ptp.c 



Initialize TSPLL after initializing PHC in ice_ptp.c instead of calling
for each product in PHC init in ice_ptp_hw.c.

Reviewed-by: default avatarMichal Kubiak <michal.kubiak@intel.com>
Reviewed-by: default avatarMilena Olech <milena.olech@intel.com>
Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Tested-by: default avatarRinitha S <sx.rinitha@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 84b86944

drivers/net/ethernet/intel/ice/ice_ptp.c

+11 −0
Original line number Diff line number Diff line
@@ -2892,6 +2892,10 @@ static int ice_ptp_rebuild_owner(struct ice_pf *pf) 
	if (err)

		return err;



	err = ice_tspll_init(hw);

	if (err)

		return err;



	/* Acquire the global hardware lock */

	if (!ice_ptp_lock(hw)) {

		err = -EBUSY;
@@ -3059,6 +3063,13 @@ static int ice_ptp_init_owner(struct ice_pf *pf) 
		return err;

	}



	err = ice_tspll_init(hw);

	if (err) {

		dev_err(ice_pf_to_dev(pf), "Failed to initialize CGU, status %d\n",

			err);

		return err;

	}



	/* Acquire the global hardware lock */

	if (!ice_ptp_lock(hw)) {

		err = -EBUSY;

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

+1 −21
Original line number Diff line number Diff line
@@ -2115,20 +2115,6 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 
	return 0;

}



/**

 * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization

 * @hw: pointer to HW struct

 *

 * Perform E825-specific PTP hardware clock initialization steps.

 *

 * Return: 0 on success, negative error code otherwise.

 */

static int ice_ptp_init_phc_e825(struct ice_hw *hw)

{

	/* Initialize the Clock Generation Unit */

	return ice_tspll_init(hw);

}



/**

 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status

 * @hw: pointer to the HW struct
@@ -2788,7 +2774,6 @@ static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 
 */

static int ice_ptp_init_phc_e82x(struct ice_hw *hw)

{

	int err;

	u32 val;



	/* Enable reading switch and PHY registers over the sideband queue */
@@ -2798,11 +2783,6 @@ static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 
	val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0);

	wr32(hw, PF_SB_REM_DEV_CTL, val);



	/* Initialize the Clock Generation Unit */

	err = ice_tspll_init(hw);

	if (err)

		return err;



	/* Set window length for all the ports */

	return ice_ptp_set_vernier_wl(hw);

}
@@ -5584,7 +5564,7 @@ int ice_ptp_init_phc(struct ice_hw *hw) 
	case ICE_MAC_GENERIC:

		return ice_ptp_init_phc_e82x(hw);

	case ICE_MAC_GENERIC_3K_E825:

		return ice_ptp_init_phc_e825(hw);

		return 0;

	default:

		return -EOPNOTSUPP;

	}

drivers/net/ethernet/intel/ice/ice_tspll.c

+5 −0
Original line number Diff line number Diff line
@@ -592,6 +592,11 @@ int ice_tspll_init(struct ice_hw *hw) 
	enum ice_clk_src clk_src;

	int err;



	/* Only E822, E823 and E825 products support TSPLL */

	if (hw->mac_type != ICE_MAC_GENERIC &&

	    hw->mac_type != ICE_MAC_GENERIC_3K_E825)

		return 0;



	tspll_freq = (enum ice_tspll_freq)ts_info->time_ref;

	clk_src = (enum ice_clk_src)ts_info->clk_src;

	if (!ice_tspll_check_params(hw, tspll_freq, clk_src))