Commit e9a09a19 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
Browse files

drm/amd/display: Allow Z8 when stutter threshold is not met 



[Why&How]
Some panels don't meet the stutter threshold (4k etc), this leads to
power regressions. Allow z8 for panels that don't meet the threshold
but support PSR/replay

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 54935663

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+7 −2
Original line number Diff line number Diff line
@@ -1085,6 +1085,9 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc 
		int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;

		bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;

		bool is_pwrseq0 = link->link_index == 0;

		bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 ||

						link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);

		bool is_replay = link && link->replay_settings.replay_feature_enabled;



		/* Don't support multi-plane configurations */

		if (stream_status->plane_count > 1)
@@ -1092,13 +1095,15 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc 


		if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)

			return DCN_ZSTATE_SUPPORT_ALLOW;

		else if (is_pwrseq0 && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr)

			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;

		else if (is_pwrseq0 && (is_psr || is_replay))

			return DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY;

		else

			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY : DCN_ZSTATE_SUPPORT_DISALLOW;

	} else {

		return DCN_ZSTATE_SUPPORT_DISALLOW;

	}



	return DCN_ZSTATE_SUPPORT_DISALLOW;

}



static void dcn20_adjust_freesync_v_startup(

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

+9 −1
Original line number Diff line number Diff line
@@ -485,6 +485,7 @@ void dcn31_calculate_wm_and_dlg_fp( 
{

	int i, pipe_idx, total_det = 0, active_hubp_count = 0;

	double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

	uint32_t cstate_enter_plus_exit_z8_ns;



	dc_assert_fp_enabled();
@@ -504,6 +505,13 @@ void dcn31_calculate_wm_and_dlg_fp( 
	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;

	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;



	cstate_enter_plus_exit_z8_ns =

		get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;



	if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_time &&

			cstate_enter_plus_exit_z8_ns < dc->debug.minimum_z8_residency_time * 1000)

		cstate_enter_plus_exit_z8_ns = dc->debug.minimum_z8_residency_time * 1000;



	/* Set A:

	 * All clocks min required

	 *
@@ -514,7 +522,7 @@ void dcn31_calculate_wm_and_dlg_fp( 
	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns;

	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;