Commit ea0bdf2b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'cxl-fixes-6.18-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl 

Pull Compute Express Link fixes from Dave Jiang:
 "A small collection of CXL fixes. In addition to some misc fixes for
  the CXL subsystem, a number of fixes for CXL extended linear cache
  support are included to make it functional again.

   - Avoid missing port component registers setup due to dport
     enumeration failure

   - Add check for no entries in cxl_feature_info to address accessing
     invalid pointer.

   - Use %pa printk format to emit resource_size_t in
     validate_region_offset()

  CXL extended linear cache support fixes:

   - Fix setup of memory resource in cxl_acpi_set_cache_size()

   - Set range param for region_res_match_cxl_range() as const
     (addresses a compile warning for match_region_by_range() fix)

   - Fix match_region_by_range() to use region_res_match_cxl_range()

   - Subtract to find an hpa_alias0 in cxl_poison events to correct the
     alias math calculation"

* tag 'cxl-fixes-6.18-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl:
  cxl/trace: Subtract to find an hpa_alias0 in cxl_poison events
  cxl/region: Use %pa printk format to emit resource_size_t
  cxl: Fix match_region_by_range() to use region_res_match_cxl_range()
  cxl: Set range param for region_res_match_cxl_range() as const
  cxl/acpi: Fix setup of memory resource in cxl_acpi_set_cache_size()
  cxl/features: Add check for no entries in cxl_feature_info
  cxl/port: Avoid missing port component registers setup
parents 2953fb65 a4bbb493

drivers/cxl/acpi.c

+1 −1
Original line number Diff line number Diff line
@@ -348,7 +348,7 @@ static int cxl_acpi_set_cache_size(struct cxl_root_decoder *cxlrd) 
	struct resource res;

	int nid, rc;



	res = DEFINE_RES(start, size, 0);

	res = DEFINE_RES_MEM(start, size);

	nid = phys_to_target_node(start);



	rc = hmat_get_extended_linear_cache_size(&res, nid, &cache_size);

drivers/cxl/core/features.c

+3 −0
Original line number Diff line number Diff line
@@ -371,6 +371,9 @@ cxl_feature_info(struct cxl_features_state *cxlfs, 
{

	struct cxl_feat_entry *feat;



	if (!cxlfs || !cxlfs->entries)

		return ERR_PTR(-EOPNOTSUPP);



	for (int i = 0; i < cxlfs->entries->num_features; i++) {

		feat = &cxlfs->entries->ent[i];

		if (uuid_equal(uuid, &feat->uuid))

drivers/cxl/core/port.c

+14 −12
Original line number Diff line number Diff line
@@ -1182,6 +1182,20 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, 
	if (rc)

		return ERR_PTR(rc);



	/*

	 * Setup port register if this is the first dport showed up. Having

	 * a dport also means that there is at least 1 active link.

	 */

	if (port->nr_dports == 1 &&

	    port->component_reg_phys != CXL_RESOURCE_NONE) {

		rc = cxl_port_setup_regs(port, port->component_reg_phys);

		if (rc) {

			xa_erase(&port->dports, (unsigned long)dport->dport_dev);

			return ERR_PTR(rc);

		}

		port->component_reg_phys = CXL_RESOURCE_NONE;

	}



	get_device(dport_dev);

	rc = devm_add_action_or_reset(host, cxl_dport_remove, dport);

	if (rc)
@@ -1200,18 +1214,6 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, 


	cxl_debugfs_create_dport_dir(dport);



	/*

	 * Setup port register if this is the first dport showed up. Having

	 * a dport also means that there is at least 1 active link.

	 */

	if (port->nr_dports == 1 &&

	    port->component_reg_phys != CXL_RESOURCE_NONE) {

		rc = cxl_port_setup_regs(port, port->component_reg_phys);

		if (rc)

			return ERR_PTR(rc);

		port->component_reg_phys = CXL_RESOURCE_NONE;

	}



	return dport;

}

drivers/cxl/core/region.c

+4 −7
Original line number Diff line number Diff line
@@ -839,7 +839,7 @@ static int match_free_decoder(struct device *dev, const void *data) 
}



static bool region_res_match_cxl_range(const struct cxl_region_params *p,

				       struct range *range)

				       const struct range *range)

{

	if (!p->res)

		return false;
@@ -3398,10 +3398,7 @@ static int match_region_by_range(struct device *dev, const void *data) 
	p = &cxlr->params;



	guard(rwsem_read)(&cxl_rwsem.region);

	if (p->res && p->res->start == r->start && p->res->end == r->end)

		return 1;



	return 0;

	return region_res_match_cxl_range(p, r);

}



static int cxl_extended_linear_cache_resize(struct cxl_region *cxlr,
@@ -3666,14 +3663,14 @@ static int validate_region_offset(struct cxl_region *cxlr, u64 offset) 


	if (offset < p->cache_size) {

		dev_err(&cxlr->dev,

			"Offset %#llx is within extended linear cache %pr\n",

			"Offset %#llx is within extended linear cache %pa\n",

			offset, &p->cache_size);

		return -EINVAL;

	}



	region_size = resource_size(p->res);

	if (offset >= region_size) {

		dev_err(&cxlr->dev, "Offset %#llx exceeds region size %pr\n",

		dev_err(&cxlr->dev, "Offset %#llx exceeds region size %pa\n",

			offset, &region_size);

		return -EINVAL;

	}

drivers/cxl/core/trace.h

+1 −1
Original line number Diff line number Diff line
@@ -1068,7 +1068,7 @@ TRACE_EVENT(cxl_poison, 
			__entry->hpa = cxl_dpa_to_hpa(cxlr, cxlmd,

						      __entry->dpa);

			if (__entry->hpa != ULLONG_MAX && cxlr->params.cache_size)

				__entry->hpa_alias0 = __entry->hpa +

				__entry->hpa_alias0 = __entry->hpa -

						      cxlr->params.cache_size;

			else

				__entry->hpa_alias0 = ULLONG_MAX;