Unverified Commit ea0e0178 authored by Yu Chien Peter Lin's avatar Yu Chien Peter Lin Committed by Palmer Dabbelt
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perf: RISC-V: Eliminate redundant interrupt enable/disable operations 



The interrupt enable/disable operations are already performed by the
IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during
enable_percpu_irq()/disable_percpu_irq(). It can be done only once.

Signed-off-by: default avatarYu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: default avatarAtish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-7-peterlin@andestech.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 95113bb7

drivers/perf/riscv_pmu_sbi.c

+0 −2
Original line number Diff line number Diff line
@@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) 
	if (riscv_pmu_use_irq) {

		cpu_hw_evt->irq = riscv_pmu_irq;

		csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));

		csr_set(CSR_IE, BIT(riscv_pmu_irq_num));

		enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);

	}
@@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) 
{

	if (riscv_pmu_use_irq) {

		disable_percpu_irq(riscv_pmu_irq);

		csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));

	}



	/* Disable all counters access for user mode now */