Commit ea1cca02 authored by Yassine Oudjana's avatar Yassine Oudjana Committed by Stephen Boyd
Browse files

dt-bindings: clock: Add MediaTek MT6735 clock and reset bindings 



Add clock definitions for the main clock and reset controllers of MT6735
(apmixedsys, topckgen, infracfg and pericfg).

Signed-off-by: default avatarYassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241017071708.38663-2-y.oudjana@protonmail.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 98619dc3

Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml

+3 −1
Original line number Diff line number Diff line
@@ -12,7 +12,8 @@ maintainers: 


description:

  The Mediatek apmixedsys controller provides PLLs to the system.

  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.

  The clock values can be found in <dt-bindings/clock/mt*-clk.h>

  and <dt-bindings/clock/mediatek,mt*-apmixedsys.h>.



properties:

  compatible:
@@ -34,6 +35,7 @@ properties: 
          - enum:

              - mediatek,mt2701-apmixedsys

              - mediatek,mt2712-apmixedsys

              - mediatek,mt6735-apmixedsys

              - mediatek,mt6765-apmixedsys

              - mediatek,mt6779-apmixed

              - mediatek,mt6795-apmixedsys

Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml

+5 −3
Original line number Diff line number Diff line
@@ -11,9 +11,10 @@ maintainers: 


description:

  The Mediatek infracfg controller provides various clocks and reset outputs

  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,

  and reset values in <dt-bindings/reset/mt*-reset.h> and

  <dt-bindings/reset/mt*-resets.h>.

  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>

  and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in

  <dt-bindings/reset/mt*-reset.h>, <dt-bindings/reset/mt*-resets.h> and

  <dt-bindings/reset/mediatek,mt*-infracfg.h>.



properties:

  compatible:
@@ -22,6 +23,7 @@ properties: 
          - enum:

              - mediatek,mt2701-infracfg

              - mediatek,mt2712-infracfg

              - mediatek,mt6735-infracfg

              - mediatek,mt6765-infracfg

              - mediatek,mt6795-infracfg

              - mediatek,mt6779-infracfg_ao

Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml

+1 −0
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@@ -20,6 +20,7 @@ properties: 
          - enum:

              - mediatek,mt2701-pericfg

              - mediatek,mt2712-pericfg

              - mediatek,mt6735-pericfg

              - mediatek,mt6765-pericfg

              - mediatek,mt6795-pericfg

              - mediatek,mt7622-pericfg

Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml

+3 −1
Original line number Diff line number Diff line
@@ -12,7 +12,8 @@ maintainers: 


description:

  The Mediatek topckgen controller provides various clocks to the system.

  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.

  The clock values can be found in <dt-bindings/clock/mt*-clk.h> and

  <dt-bindings/clock/mediatek,mt*-topckgen.h>.



properties:

  compatible:
@@ -31,6 +32,7 @@ properties: 
          - enum:

              - mediatek,mt2701-topckgen

              - mediatek,mt2712-topckgen

              - mediatek,mt6735-topckgen

              - mediatek,mt6765-topckgen

              - mediatek,mt6779-topckgen

              - mediatek,mt6795-topckgen

MAINTAINERS

+12 −0
Original line number Diff line number Diff line
@@ -14528,6 +14528,18 @@ S: Maintained 
F:	Documentation/devicetree/bindings/mmc/mtk-sd.yaml

F:	drivers/mmc/host/mtk-sd.c









MEDIATEK MT6735 CLOCK & RESET DRIVERS









M:	Yassine Oudjana <y.oudjana@protonmail.com>









L:	linux-clk@vger.kernel.org









L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)









S:	Maintained









F:	include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h









F:	include/dt-bindings/clock/mediatek,mt6735-infracfg.h









F:	include/dt-bindings/clock/mediatek,mt6735-pericfg.h









F:	include/dt-bindings/clock/mediatek,mt6735-topckgen.h









F:	include/dt-bindings/reset/mediatek,mt6735-infracfg.h









F:	include/dt-bindings/reset/mediatek,mt6735-pericfg.h

















MEDIATEK MT76 WIRELESS LAN DRIVER









M:	Felix Fietkau <nbd@nbd.name>









M:	Lorenzo Bianconi <lorenzo@kernel.org>