Commit ea2d3612 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: rework plane CSC setting 



Rework the code flushing CSC settings for the plane. Separate out the
pipe and pipe_cfg as a preparation for r_pipe support.

Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/527347/
Link: https://lore.kernel.org/r/20230316161653.4106395-25-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 6d7e1ca7

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

+27 −20
Original line number Diff line number Diff line
@@ -577,29 +577,19 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 
	{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},

};



static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt)

static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,

						    const struct dpu_format *fmt)

{

	struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state);

	const struct dpu_csc_cfg *csc_ptr;



	if (!pdpu) {

		DPU_ERROR("invalid plane\n");

		return NULL;

	}



	if (!DPU_FORMAT_IS_YUV(fmt))

		return NULL;



	if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe.sspp->cap->features)

	if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features)

		csc_ptr = &dpu_csc10_YUV2RGB_601L;

	else

		csc_ptr = &dpu_csc_YUV2RGB_601L;



	DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",

			csc_ptr->csc_mv[0],

			csc_ptr->csc_mv[1],

			csc_ptr->csc_mv[2]);



	return csc_ptr;

}
@@ -1052,6 +1042,28 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, 
	return 0;

}



static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)

{

	const struct dpu_format *format =

		to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb));

	const struct dpu_csc_cfg *csc_ptr;



	if (!pipe->sspp || !pipe->sspp->ops.setup_csc)

		return;



	csc_ptr = _dpu_plane_get_csc(pipe, format);

	if (!csc_ptr)

		return;



	DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",

			csc_ptr->csc_mv[0],

			csc_ptr->csc_mv[1],

			csc_ptr->csc_mv[2]);



	pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr);



}



void dpu_plane_flush(struct drm_plane *plane)

{

	struct dpu_plane *pdpu;
@@ -1075,13 +1087,8 @@ void dpu_plane_flush(struct drm_plane *plane) 
	else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)

		/* force 100% alpha */

		_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);

	else if (pstate->pipe.sspp && pstate->pipe.sspp->ops.setup_csc) {

		const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));

		const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);



		if (csc_ptr)

			pstate->pipe.sspp->ops.setup_csc(pstate->pipe.sspp, csc_ptr);

	}

	else

		dpu_plane_flush_csc(pdpu, &pstate->pipe);



	/* flag h/w flush complete */

	if (plane->state)