Commit ea3d3546 authored by Suman Kumar Chakraborty's avatar Suman Kumar Chakraborty Committed by Herbert Xu
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crypto: qat - add macro to write 64-bit values to registers 



Introduce the ADF_CSR_WR_LO_HI macro to simplify writing a 64-bit values
to hardware registers.

This macro works by splitting the 64-bit value into two 32-bit segments,
which are then written separately to the specified lower and upper
register offsets.

Update the adf_gen4_set_ssm_wdtimer() function to utilize this newly
introduced macro.

Signed-off-by: default avatarSuman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent d2d072a3

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

+10 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include <linux/ratelimit.h>

#include <linux/types.h>

#include <linux/qat/qat_mig_dev.h>

#include <linux/wordpart.h>

#include "adf_cfg_common.h"

#include "adf_rl.h"

#include "adf_telemetry.h"
@@ -371,6 +372,15 @@ struct adf_hw_device_data { 
/* CSR write macro */

#define ADF_CSR_WR(csr_base, csr_offset, val) \

	__raw_writel(val, csr_base + csr_offset)

/*

 * CSR write macro to handle cases where the high and low

 * offsets are sparsely located.

 */

#define ADF_CSR_WR64_LO_HI(csr_base, csr_low_offset, csr_high_offset, val)	\

do {										\

	ADF_CSR_WR(csr_base, csr_low_offset, lower_32_bits(val));		\

	ADF_CSR_WR(csr_base, csr_high_offset, upper_32_bits(val));		\

} while (0)



/* CSR read macro */

#define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

+6 −24
Original line number Diff line number Diff line
@@ -135,36 +135,18 @@ int adf_gen4_init_device(struct adf_accel_dev *accel_dev) 
}

EXPORT_SYMBOL_GPL(adf_gen4_init_device);



static inline void adf_gen4_unpack_ssm_wdtimer(u64 value, u32 *upper,

					       u32 *lower)

{

	*lower = lower_32_bits(value);

	*upper = upper_32_bits(value);

}



void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)

{

	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);

	u64 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;

	u64 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;

	u32 ssm_wdt_pke_high = 0;

	u32 ssm_wdt_pke_low = 0;

	u32 ssm_wdt_high = 0;

	u32 ssm_wdt_low = 0;



	/* Convert 64bit WDT timer value into 32bit values for

	 * mmio write to 32bit CSRs.

	 */

	adf_gen4_unpack_ssm_wdtimer(timer_val, &ssm_wdt_high, &ssm_wdt_low);

	adf_gen4_unpack_ssm_wdtimer(timer_val_pke, &ssm_wdt_pke_high,

				    &ssm_wdt_pke_low);



	/* Enable WDT for sym and dc */

	ADF_CSR_WR(pmisc_addr, ADF_SSMWDTL_OFFSET, ssm_wdt_low);

	ADF_CSR_WR(pmisc_addr, ADF_SSMWDTH_OFFSET, ssm_wdt_high);

	/* Enable WDT for pke */

	ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ssm_wdt_pke_low);

	ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEH_OFFSET, ssm_wdt_pke_high);

	/* Enable watchdog timer for sym and dc */

	ADF_CSR_WR64_LO_HI(pmisc_addr, ADF_SSMWDTL_OFFSET, ADF_SSMWDTH_OFFSET, timer_val);



	/* Enable watchdog timer for pke */

	ADF_CSR_WR64_LO_HI(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ADF_SSMWDTPKEH_OFFSET,

			   timer_val_pke);

}

EXPORT_SYMBOL_GPL(adf_gen4_set_ssm_wdtimer);