Commit ea6398a5 authored by Michael Neuling's avatar Michael Neuling Committed by Anup Patel
Browse files

RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit 



This doesn't cause a problem currently as HVIEN isn't used elsewhere
yet. Found by inspection.

Signed-off-by: default avatarMichael Neuling <michaelneuling@tenstorrent.com>
Fixes: 16b0bde9 ("RISC-V: KVM: Add perf sampling support for guests")
Reviewed-by: default avatarAtish Patra <atishp@rivosinc.com>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20241127041840.419940-1-michaelneuling@tenstorrent.com


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 40384c84

arch/riscv/kvm/aia.c

+1 −1
Original line number Diff line number Diff line
@@ -590,7 +590,7 @@ void kvm_riscv_aia_enable(void) 
	csr_set(CSR_HIE, BIT(IRQ_S_GEXT));

	/* Enable IRQ filtering for overflow interrupt only if sscofpmf is present */

	if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF))

		csr_write(CSR_HVIEN, BIT(IRQ_PMU_OVF));

		csr_set(CSR_HVIEN, BIT(IRQ_PMU_OVF));

}



void kvm_riscv_aia_disable(void)