Commit ea69f782 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-fixes-2024-02-15' of https://gitlab.freedesktop.org/drm/msm into drm-fixes 



Fixes for v6.8-rc5

GPU:
- dmabuf vmap fix
- a610 UBWC corruption fix (incorrect hbb)
- revert a commit that was making GPU recovery unreliable
- tlb invalidation fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGszDSiw66+a=ttBr-hat+zrcBtfc_cZ4LQqXu89DJ0UeQ@mail.gmail.com
parents 44395701 8c7bfd82

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -1287,7 +1287,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 
	gpu->ubwc_config.highest_bank_bit = 15;



	if (adreno_is_a610(gpu)) {

		gpu->ubwc_config.highest_bank_bit = 14;

		gpu->ubwc_config.highest_bank_bit = 13;

		gpu->ubwc_config.min_acc_len = 1;

		gpu->ubwc_config.ubwc_mode = 1;

	}

drivers/gpu/drm/msm/msm_gem_prime.c

+2 −2
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map) 
{

	void *vaddr;



	vaddr = msm_gem_get_vaddr(obj);

	vaddr = msm_gem_get_vaddr_locked(obj);

	if (IS_ERR(vaddr))

		return PTR_ERR(vaddr);

	iosys_map_set_vaddr(map, vaddr);
@@ -36,7 +36,7 @@ int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map) 


void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map)

{

	msm_gem_put_vaddr(obj);

	msm_gem_put_vaddr_locked(obj);

}



struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,

drivers/gpu/drm/msm/msm_gpu.c

+5 −6
Original line number Diff line number Diff line
@@ -751,12 +751,14 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 
	struct msm_ringbuffer *ring = submit->ring;

	unsigned long flags;



	pm_runtime_get_sync(&gpu->pdev->dev);

	WARN_ON(!mutex_is_locked(&gpu->lock));



	mutex_lock(&gpu->lock);

	pm_runtime_get_sync(&gpu->pdev->dev);



	msm_gpu_hw_init(gpu);



	submit->seqno = submit->hw_fence->seqno;



	update_sw_cntrs(gpu);



	/*
@@ -781,11 +783,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 
	gpu->funcs->submit(gpu, submit);

	gpu->cur_ctx_seqno = submit->queue->ctx->seqno;



	hangcheck_timer_reset(gpu);



	mutex_unlock(&gpu->lock);



	pm_runtime_put(&gpu->pdev->dev);

	hangcheck_timer_reset(gpu);

}



/*

drivers/gpu/drm/msm/msm_iommu.c

+29 −3
Original line number Diff line number Diff line
@@ -21,6 +21,8 @@ struct msm_iommu_pagetable { 
	struct msm_mmu base;

	struct msm_mmu *parent;

	struct io_pgtable_ops *pgtbl_ops;

	const struct iommu_flush_ops *tlb;

	struct device *iommu_dev;

	unsigned long pgsize_bitmap;	/* Bitmap of page sizes in use */

	phys_addr_t ttbr;

	u32 asid;
@@ -201,11 +203,33 @@ static const struct msm_mmu_funcs pagetable_funcs = { 


static void msm_iommu_tlb_flush_all(void *cookie)

{

	struct msm_iommu_pagetable *pagetable = cookie;

	struct adreno_smmu_priv *adreno_smmu;



	if (!pm_runtime_get_if_in_use(pagetable->iommu_dev))

		return;



	adreno_smmu = dev_get_drvdata(pagetable->parent->dev);



	pagetable->tlb->tlb_flush_all((void *)adreno_smmu->cookie);



	pm_runtime_put_autosuspend(pagetable->iommu_dev);

}



static void msm_iommu_tlb_flush_walk(unsigned long iova, size_t size,

		size_t granule, void *cookie)

{

	struct msm_iommu_pagetable *pagetable = cookie;

	struct adreno_smmu_priv *adreno_smmu;



	if (!pm_runtime_get_if_in_use(pagetable->iommu_dev))

		return;



	adreno_smmu = dev_get_drvdata(pagetable->parent->dev);



	pagetable->tlb->tlb_flush_walk(iova, size, granule, (void *)adreno_smmu->cookie);



	pm_runtime_put_autosuspend(pagetable->iommu_dev);

}



static void msm_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,
@@ -213,7 +237,7 @@ static void msm_iommu_tlb_add_page(struct iommu_iotlb_gather *gather, 
{

}



static const struct iommu_flush_ops null_tlb_ops = {

static const struct iommu_flush_ops tlb_ops = {

	.tlb_flush_all = msm_iommu_tlb_flush_all,

	.tlb_flush_walk = msm_iommu_tlb_flush_walk,

	.tlb_add_page = msm_iommu_tlb_add_page,
@@ -254,10 +278,10 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) 


	/* The incoming cfg will have the TTBR1 quirk enabled */

	ttbr0_cfg.quirks &= ~IO_PGTABLE_QUIRK_ARM_TTBR1;

	ttbr0_cfg.tlb = &null_tlb_ops;

	ttbr0_cfg.tlb = &tlb_ops;



	pagetable->pgtbl_ops = alloc_io_pgtable_ops(ARM_64_LPAE_S1,

		&ttbr0_cfg, iommu->domain);

		&ttbr0_cfg, pagetable);



	if (!pagetable->pgtbl_ops) {

		kfree(pagetable);
@@ -279,6 +303,8 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) 


	/* Needed later for TLB flush */

	pagetable->parent = parent;

	pagetable->tlb = ttbr1_cfg->tlb;

	pagetable->iommu_dev = ttbr1_cfg->iommu_dev;

	pagetable->pgsize_bitmap = ttbr0_cfg.pgsize_bitmap;

	pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr;

drivers/gpu/drm/msm/msm_ringbuffer.c

+5 −2
Original line number Diff line number Diff line
@@ -21,8 +21,6 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) 


	msm_fence_init(submit->hw_fence, fctx);



	submit->seqno = submit->hw_fence->seqno;



	mutex_lock(&priv->lru.lock);



	for (i = 0; i < submit->nr_bos; i++) {
@@ -35,8 +33,13 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) 


	mutex_unlock(&priv->lru.lock);



	/* TODO move submit path over to using a per-ring lock.. */

	mutex_lock(&gpu->lock);



	msm_gpu_submit(gpu, submit);



	mutex_unlock(&gpu->lock);



	return dma_fence_get(submit->hw_fence);

}