Commit ea7d0d60 authored by Paolo Abeni's avatar Paolo Abeni
Browse files

Merge branch 'add-cn20k-nix-and-npa-contexts' 

Subbaraya Sundeep says:

====================
Add CN20K NIX and NPA contexts

The hardware contexts of blocks NIX and NPA in CN20K silicon are
different than that of previous silicons CN10K and CN9XK. This
patchset adds the new contexts of CN20K in AF and PF drivers.
A new mailbox for enqueuing contexts to hardware is added.

Patch 1 simplifies context writing and reading by using max context
size supported by hardware instead of using each context size.
Patch 2 and 3 adds NIX block contexts in AF driver and extends
debugfs to display those new contexts
Patch 4 and 5 adds NPA block contexts in AF driver and extends
debugfs to display those new contexts
Patch 6 omits NDC configuration since CN20K NPA does not use NDC
for caching its contexts
Patch 7 and 8 uses the new NIX and NPA contexts in PF/VF driver.
Patch 9, 10 and 11 are to support more bandwidth profiles present in
CN20K for RX ratelimiting and to display new profiles in debugfs

v3: https://lore.kernel.org/all/1752772063-6160-1-git-send-email-sbhatta@marvell.com/
====================

Link: https://patch.msgid.link/1761388367-16579-1-git-send-email-sbhatta@marvell.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parents 1bae0fd9 33d8a1f4

drivers/net/ethernet/marvell/octeontx2/af/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -12,4 +12,5 @@ rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \ 
		  rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \

		  rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \

		  rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o \

		  rvu_rep.o cn20k/mbox_init.o
 
		  rvu_rep.o cn20k/mbox_init.o cn20k/nix.o cn20k/debugfs.o \

		  cn20k/npa.o

drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c

0 → 100644
+218 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Marvell RVU Admin Function driver

 *

 * Copyright (C) 2024 Marvell.

 *

 */



#include <linux/fs.h>

#include <linux/debugfs.h>

#include <linux/module.h>

#include <linux/pci.h>



#include "struct.h"

#include "debugfs.h"



void print_nix_cn20k_sq_ctx(struct seq_file *m,

			    struct nix_cn20k_sq_ctx_s *sq_ctx)

{

	seq_printf(m, "W0: ena \t\t\t%d\nW0: qint_idx \t\t\t%d\n",

		   sq_ctx->ena, sq_ctx->qint_idx);

	seq_printf(m, "W0: substream \t\t\t0x%03x\nW0: sdp_mcast \t\t\t%d\n",

		   sq_ctx->substream, sq_ctx->sdp_mcast);

	seq_printf(m, "W0: cq \t\t\t\t%d\nW0: sqe_way_mask \t\t%d\n\n",

		   sq_ctx->cq, sq_ctx->sqe_way_mask);



	seq_printf(m, "W1: smq \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: xoff\t\t\t%d\n",

		   sq_ctx->smq, sq_ctx->cq_ena, sq_ctx->xoff);

	seq_printf(m, "W1: sso_ena \t\t\t%d\nW1: smq_rr_weight\t\t%d\n",

		   sq_ctx->sso_ena, sq_ctx->smq_rr_weight);

	seq_printf(m, "W1: default_chan\t\t%d\nW1: sqb_count\t\t\t%d\n\n",

		   sq_ctx->default_chan, sq_ctx->sqb_count);



	seq_printf(m, "W1: smq_rr_count_lb \t\t%d\n", sq_ctx->smq_rr_count_lb);

	seq_printf(m, "W2: smq_rr_count_ub \t\t%d\n", sq_ctx->smq_rr_count_ub);

	seq_printf(m, "W2: sqb_aura \t\t\t%d\nW2: sq_int \t\t\t%d\n",

		   sq_ctx->sqb_aura, sq_ctx->sq_int);

	seq_printf(m, "W2: sq_int_ena \t\t\t%d\nW2: sqe_stype \t\t\t%d\n",

		   sq_ctx->sq_int_ena, sq_ctx->sqe_stype);



	seq_printf(m, "W3: max_sqe_size\t\t%d\nW3: cq_limit\t\t\t%d\n",

		   sq_ctx->max_sqe_size, sq_ctx->cq_limit);

	seq_printf(m, "W3: lmt_dis \t\t\t%d\nW3: mnq_dis \t\t\t%d\n",

		   sq_ctx->lmt_dis, sq_ctx->mnq_dis);

	seq_printf(m, "W3: smq_next_sq\t\t\t%d\nW3: smq_lso_segnum\t\t%d\n",

		   sq_ctx->smq_next_sq, sq_ctx->smq_lso_segnum);

	seq_printf(m, "W3: tail_offset \t\t%d\nW3: smenq_offset\t\t%d\n",

		   sq_ctx->tail_offset, sq_ctx->smenq_offset);

	seq_printf(m, "W3: head_offset\t\t\t%d\nW3: smenq_next_sqb_vld\t\t%d\n\n",

		   sq_ctx->head_offset, sq_ctx->smenq_next_sqb_vld);



	seq_printf(m, "W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d\n",

		   sq_ctx->smq_next_sq_vld, sq_ctx->smq_pend);

	seq_printf(m, "W4: next_sqb \t\t\t%llx\n\n", sq_ctx->next_sqb);

	seq_printf(m, "W5: tail_sqb \t\t\t%llx\n\n", sq_ctx->tail_sqb);

	seq_printf(m, "W6: smenq_sqb \t\t\t%llx\n\n", sq_ctx->smenq_sqb);

	seq_printf(m, "W7: smenq_next_sqb \t\t%llx\n\n",

		   sq_ctx->smenq_next_sqb);



	seq_printf(m, "W8: head_sqb\t\t\t%llx\n\n", sq_ctx->head_sqb);



	seq_printf(m, "W9: vfi_lso_total\t\t%d\n", sq_ctx->vfi_lso_total);

	seq_printf(m, "W9: vfi_lso_sizem1\t\t%d\nW9: vfi_lso_sb\t\t\t%d\n",

		   sq_ctx->vfi_lso_sizem1, sq_ctx->vfi_lso_sb);

	seq_printf(m, "W9: vfi_lso_mps\t\t\t%d\nW9: vfi_lso_vlan0_ins_ena\t%d\n",

		   sq_ctx->vfi_lso_mps, sq_ctx->vfi_lso_vlan0_ins_ena);

	seq_printf(m, "W9: vfi_lso_vlan1_ins_ena\t%d\nW9: vfi_lso_vld \t\t%d\n\n",

		   sq_ctx->vfi_lso_vld, sq_ctx->vfi_lso_vlan1_ins_ena);



	seq_printf(m, "W10: scm_lso_rem \t\t%llu\n\n",

		   (u64)sq_ctx->scm_lso_rem);

	seq_printf(m, "W11: octs \t\t\t%llu\n\n", (u64)sq_ctx->octs);

	seq_printf(m, "W12: pkts \t\t\t%llu\n\n", (u64)sq_ctx->pkts);

	seq_printf(m, "W13: aged_drop_octs \t\t\t%llu\n\n",

		   (u64)sq_ctx->aged_drop_octs);

	seq_printf(m, "W13: aged_drop_pkts \t\t\t%llu\n\n",

		   (u64)sq_ctx->aged_drop_pkts);

	seq_printf(m, "W14: dropped_octs \t\t%llu\n\n",

		   (u64)sq_ctx->dropped_octs);

	seq_printf(m, "W15: dropped_pkts \t\t%llu\n\n",

		   (u64)sq_ctx->dropped_pkts);

}



void print_nix_cn20k_cq_ctx(struct seq_file *m,

			    struct nix_cn20k_aq_enq_rsp *rsp)

{

	struct nix_cn20k_cq_ctx_s *cq_ctx = &rsp->cq;



	seq_printf(m, "W0: base \t\t\t%llx\n\n", cq_ctx->base);



	seq_printf(m, "W1: wrptr \t\t\t%llx\n", (u64)cq_ctx->wrptr);

	seq_printf(m, "W1: avg_con \t\t\t%d\nW1: cint_idx \t\t\t%d\n",

		   cq_ctx->avg_con, cq_ctx->cint_idx);

	seq_printf(m, "W1: cq_err \t\t\t%d\nW1: qint_idx \t\t\t%d\n",

		   cq_ctx->cq_err, cq_ctx->qint_idx);

	seq_printf(m, "W1: bpid \t\t\t%d\nW1: bp_ena \t\t\t%d\n\n",

		   cq_ctx->bpid, cq_ctx->bp_ena);



	seq_printf(m, "W1: lbpid_high \t\t\t0x%03x\n", cq_ctx->lbpid_high);

	seq_printf(m, "W1: lbpid_med \t\t\t0x%03x\n", cq_ctx->lbpid_med);

	seq_printf(m, "W1: lbpid_low \t\t\t0x%03x\n", cq_ctx->lbpid_low);

	seq_printf(m, "(W1: lbpid) \t\t\t0x%03x\n",

		   cq_ctx->lbpid_high << 6 | cq_ctx->lbpid_med << 3 |

		   cq_ctx->lbpid_low);

	seq_printf(m, "W1: lbp_ena \t\t\t\t%d\n\n", cq_ctx->lbp_ena);



	seq_printf(m, "W2: update_time \t\t%d\nW2:avg_level \t\t\t%d\n",

		   cq_ctx->update_time, cq_ctx->avg_level);

	seq_printf(m, "W2: head \t\t\t%d\nW2:tail \t\t\t%d\n\n",

		   cq_ctx->head, cq_ctx->tail);



	seq_printf(m, "W3: cq_err_int_ena \t\t%d\nW3:cq_err_int \t\t\t%d\n",

		   cq_ctx->cq_err_int_ena, cq_ctx->cq_err_int);

	seq_printf(m, "W3: qsize \t\t\t%d\nW3:stashing \t\t\t%d\n",

		   cq_ctx->qsize, cq_ctx->stashing);



	seq_printf(m, "W3: caching \t\t\t%d\n", cq_ctx->caching);

	seq_printf(m, "W3: lbp_frac \t\t\t%d\n", cq_ctx->lbp_frac);

	seq_printf(m, "W3: stash_thresh \t\t\t%d\n",

		   cq_ctx->stash_thresh);



	seq_printf(m, "W3: msh_valid \t\t\t%d\nW3:msh_dst \t\t\t%d\n",

		   cq_ctx->msh_valid, cq_ctx->msh_dst);



	seq_printf(m, "W3: cpt_drop_err_en \t\t\t%d\n",

		   cq_ctx->cpt_drop_err_en);

	seq_printf(m, "W3: ena \t\t\t%d\n",

		   cq_ctx->ena);

	seq_printf(m, "W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d\n",

		   cq_ctx->drop_ena, cq_ctx->drop);

	seq_printf(m, "W3: bp \t\t\t\t%d\n\n", cq_ctx->bp);



	seq_printf(m, "W4: lbpid_ext \t\t\t\t%d\n\n", cq_ctx->lbpid_ext);

	seq_printf(m, "W4: bpid_ext \t\t\t\t%d\n\n", cq_ctx->bpid_ext);

}



void print_npa_cn20k_aura_ctx(struct seq_file *m,

			      struct npa_cn20k_aq_enq_rsp *rsp)

{

	struct npa_cn20k_aura_s *aura = &rsp->aura;



	seq_printf(m, "W0: Pool addr\t\t%llx\n", aura->pool_addr);



	seq_printf(m, "W1: ena\t\t\t%d\nW1: pool caching\t%d\n",

		   aura->ena, aura->pool_caching);

	seq_printf(m, "W1: avg con\t\t%d\n", aura->avg_con);

	seq_printf(m, "W1: pool drop ena\t%d\nW1: aura drop ena\t%d\n",

		   aura->pool_drop_ena, aura->aura_drop_ena);

	seq_printf(m, "W1: bp_ena\t\t%d\nW1: aura drop\t\t%d\n",

		   aura->bp_ena, aura->aura_drop);

	seq_printf(m, "W1: aura shift\t\t%d\nW1: avg_level\t\t%d\n",

		   aura->shift, aura->avg_level);



	seq_printf(m, "W2: count\t\t%llu\nW2: nix_bpid\t\t%d\n",

		   (u64)aura->count, aura->bpid);



	seq_printf(m, "W3: limit\t\t%llu\nW3: bp\t\t\t%d\nW3: fc_ena\t\t%d\n",

		   (u64)aura->limit, aura->bp, aura->fc_ena);



	seq_printf(m, "W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d\n",

		   aura->fc_up_crossing, aura->fc_stype);

	seq_printf(m, "W3: fc_hyst_bits\t%d\n", aura->fc_hyst_bits);



	seq_printf(m, "W4: fc_addr\t\t%llx\n", aura->fc_addr);



	seq_printf(m, "W5: pool_drop\t\t%d\nW5: update_time\t\t%d\n",

		   aura->pool_drop, aura->update_time);

	seq_printf(m, "W5: err_int \t\t%d\nW5: err_int_ena\t\t%d\n",

		   aura->err_int, aura->err_int_ena);

	seq_printf(m, "W5: thresh_int\t\t%d\nW5: thresh_int_ena \t%d\n",

		   aura->thresh_int, aura->thresh_int_ena);

	seq_printf(m, "W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d\n",

		   aura->thresh_up, aura->thresh_qint_idx);

	seq_printf(m, "W5: err_qint_idx \t%d\n", aura->err_qint_idx);



	seq_printf(m, "W6: thresh\t\t%llu\n", (u64)aura->thresh);

	seq_printf(m, "W6: fc_msh_dst\t\t%d\n", aura->fc_msh_dst);

}



void print_npa_cn20k_pool_ctx(struct seq_file *m,

			      struct npa_cn20k_aq_enq_rsp *rsp)

{

	struct npa_cn20k_pool_s *pool = &rsp->pool;



	seq_printf(m, "W0: Stack base\t\t%llx\n", pool->stack_base);



	seq_printf(m, "W1: ena \t\t%d\nW1: nat_align \t\t%d\n",

		   pool->ena, pool->nat_align);

	seq_printf(m, "W1: stack_caching\t%d\n",

		   pool->stack_caching);

	seq_printf(m, "W1: buf_offset\t\t%d\nW1: buf_size\t\t%d\n",

		   pool->buf_offset, pool->buf_size);



	seq_printf(m, "W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n",

		   pool->stack_max_pages, pool->stack_pages);



	seq_printf(m, "W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d\n",

		   pool->stack_offset, pool->shift, pool->avg_level);

	seq_printf(m, "W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d\n",

		   pool->avg_con, pool->fc_ena, pool->fc_stype);

	seq_printf(m, "W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d\n",

		   pool->fc_hyst_bits, pool->fc_up_crossing);

	seq_printf(m, "W4: update_time\t\t%d\n", pool->update_time);



	seq_printf(m, "W5: fc_addr\t\t%llx\n", pool->fc_addr);



	seq_printf(m, "W6: ptr_start\t\t%llx\n", pool->ptr_start);



	seq_printf(m, "W7: ptr_end\t\t%llx\n", pool->ptr_end);



	seq_printf(m, "W8: err_int\t\t%d\nW8: err_int_ena\t\t%d\n",

		   pool->err_int, pool->err_int_ena);

	seq_printf(m, "W8: thresh_int\t\t%d\n", pool->thresh_int);

	seq_printf(m, "W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d\n",

		   pool->thresh_int_ena, pool->thresh_up);

	seq_printf(m, "W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n",

		   pool->thresh_qint_idx, pool->err_qint_idx);

	seq_printf(m, "W8: fc_msh_dst\t\t%d\n", pool->fc_msh_dst);

}

drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h

0 → 100644
+28 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Marvell OcteonTx2 CGX driver

 *

 * Copyright (C) 2024 Marvell.

 *

 */



#ifndef DEBUFS_H

#define DEBUFS_H



#include <linux/fs.h>

#include <linux/debugfs.h>

#include <linux/module.h>

#include <linux/pci.h>



#include "struct.h"

#include "../mbox.h"



void print_nix_cn20k_sq_ctx(struct seq_file *m,

			    struct nix_cn20k_sq_ctx_s *sq_ctx);

void print_nix_cn20k_cq_ctx(struct seq_file *m,

			    struct nix_cn20k_aq_enq_rsp *rsp);

void print_npa_cn20k_aura_ctx(struct seq_file *m,

			      struct npa_cn20k_aq_enq_rsp *rsp);

void print_npa_cn20k_pool_ctx(struct seq_file *m,

			      struct npa_cn20k_aq_enq_rsp *rsp);



#endif

drivers/net/ethernet/marvell/octeontx2/af/cn20k/nix.c

0 → 100644
+20 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Marvell RVU Admin Function driver

 *

 * Copyright (C) 2024 Marvell.

 *

 */



#include <linux/module.h>

#include <linux/pci.h>



#include "struct.h"

#include "../rvu.h"



int rvu_mbox_handler_nix_cn20k_aq_enq(struct rvu *rvu,

				      struct nix_cn20k_aq_enq_req *req,

				      struct nix_cn20k_aq_enq_rsp *rsp)

{

	return rvu_nix_aq_enq_inst(rvu, (struct nix_aq_enq_req *)req,

				  (struct nix_aq_enq_rsp *)rsp);

}

drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c

0 → 100644
+21 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Marvell RVU Admin Function driver

 *

 * Copyright (C) 2024 Marvell.

 *

 */



#include <linux/module.h>

#include <linux/pci.h>



#include "struct.h"

#include "../rvu.h"



int rvu_mbox_handler_npa_cn20k_aq_enq(struct rvu *rvu,

				      struct npa_cn20k_aq_enq_req *req,

				      struct npa_cn20k_aq_enq_rsp *rsp)

{

	return rvu_npa_aq_enq_inst(rvu, (struct npa_aq_enq_req *)req,

				   (struct npa_aq_enq_rsp *)rsp);

}

EXPORT_SYMBOL(rvu_mbox_handler_npa_cn20k_aq_enq);