Commit ea87c553 authored by Jeremy Linton's avatar Jeremy Linton Committed by Will Deacon
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arm64: probes: Fix incorrect bl/blr address and register usage 



The pt_regs registers are 64-bit on arm64, and should be u64 when
manipulated. Correct this so that we aren't truncating the address
during br/blr sequences.

Fixes: efb07ac5 ("arm64: probes: Add GCS support to bl/blr/ret")
Signed-off-by: default avatarJeremy Linton <jeremy.linton@arm.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent ba1afc94

arch/arm64/kernel/probes/simulate-insn.c

+2 −2
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ void __kprobes 
simulate_br_blr(u32 opcode, long addr, struct pt_regs *regs)

{

	int xn = (opcode >> 5) & 0x1f;

	int b_target = get_x_reg(regs, xn);

	u64 b_target = get_x_reg(regs, xn);



	if (((opcode >> 21) & 0x3) == 1)

		if (update_lr(regs, addr + 4))
@@ -160,7 +160,7 @@ simulate_ret(u32 opcode, long addr, struct pt_regs *regs) 
	u64 ret_addr;

	int err = 0;

	int xn = (opcode >> 5) & 0x1f;

	unsigned long r_target = get_x_reg(regs, xn);

	u64 r_target = get_x_reg(regs, xn);



	if (user_mode(regs) && task_gcs_el0_enabled(current)) {

		ret_addr = pop_user_gcs(&err);