Commit eaa9d886 authored by Serge Semin's avatar Serge Semin Committed by Lorenzo Pieralisi
Browse files

dt-bindings: PCI: dwc: Add max-link-speed common property 

In accordance with [1] DW PCIe controllers support up to Gen5 link speed.
Let's add the max-link-speed property upper bound to 5 then. The DT
bindings of the particular devices are expected to setup more strict
constraint on that parameter.

[1] Synopsys DesignWare Cores PCI Express Controller Databook, Version
5.40a, March 2019, p. 27

Link: https://lore.kernel.org/r/20221113191301.5526-7-Sergey.Semin@baikalelectronics.ru


Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent 87559636

Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml

+3 −0
Original line number Diff line number Diff line
@@ -54,6 +54,9 @@ properties: 
      the peripheral devices available on the PCIe bus.

    maxItems: 1



  max-link-speed:

    maximum: 5



  num-lanes:

    description:

      Number of PCIe link lanes to use. Can be omitted if the already brought

Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

+2 −0
Original line number Diff line number Diff line
@@ -55,4 +55,6 @@ examples: 


      phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>;

      phy-names = "pcie0", "pcie1", "pcie2", "pcie3";



      max-link-speed = <3>;

    };

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

+1 −0
Original line number Diff line number Diff line
@@ -74,4 +74,5 @@ examples: 
      phy-names = "pcie";



      num-lanes = <1>;

      max-link-speed = <3>;

    };