Commit eaca33df authored by Juha Yrjola's avatar Juha Yrjola Committed by Tony Lindgren
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ARM: OMAP: Add write memory barriers to OMAP2 clock code 



After adjusting clock parameters, OMAP2 CPUs need a memory
barrier to make sure the changes go into effect immediately.
Otherwise bad things will happen if we try to access the
peripheral whose clock is just being enabled.

Signed-off-by: default avatarJuha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent dbab288b

arch/arm/mach-omap2/clock.c

+10 −4
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ static int _omap2_clk_enable(struct clk * clk) 
	regval32 = __raw_readl(clk->enable_reg);

	regval32 |= (1 << clk->enable_bit);

	__raw_writel(regval32, clk->enable_reg);

	wmb();



	return 0;

}
@@ -168,6 +169,7 @@ static void _omap2_clk_disable(struct clk *clk) 
	regval32 = __raw_readl(clk->enable_reg);

	regval32 &= ~(1 << clk->enable_bit);

	__raw_writel(regval32, clk->enable_reg);

	wmb();

}



static int omap2_clk_enable(struct clk *clk)
@@ -697,12 +699,14 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 
		reg_val = __raw_readl(reg);

		reg_val &= ~(field_mask << div_off);

		reg_val |= (field_val << div_off);



		__raw_writel(reg_val, reg);

		wmb();

		clk->rate = clk->parent->rate / field_val;



		if (clk->flags & DELAYED_APP)

		if (clk->flags & DELAYED_APP) {

			__raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);

			wmb();

		}

		ret = 0;

	} else if (clk->set_rate != 0)

		ret = clk->set_rate(clk, rate);
@@ -838,10 +842,12 @@ static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 
		reg_val = __raw_readl(reg) & ~(field_mask << src_off);

		reg_val |= (field_val << src_off);

		__raw_writel(reg_val, reg);

		wmb();



		if (clk->flags & DELAYED_APP)

		if (clk->flags & DELAYED_APP) {

			__raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);



			wmb();

		}

		if (clk->usecount > 0)

			_omap2_clk_enable(clk);