Commit eafd95ea authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "An especially linear and sparse improvement and new drivers release.
  Nothing exciting. The biggest change in Bartosz changes to make
  gpiochip set/get calls return error codes (something we should have
  fixed ages ago but is now finally getting fixed.)

  Core changes:

   - Add the devres devm_pinctrl_register_mappings() call that can
     register some pin control machine mappings and have them go away
     with the associated device

  New drivers:

   - Support for the Mediatek MT6893 and MT8196 SoCs

   - Support for the Renesas RZ/V2N SoC

   - Support for the NXP Freescale i.MX943 SoC

  Improvements:

   - Per-SoC suspend/resume callbacks in the Samsung drivers

   - Set all pins as input (High-Z) at probe in the MCP23S08 driver

   - Switch most GPIO chips to use the setters/getters with a return
     value

   - EGPIO support in the Qualcomm QCM2290 driver

   - Fix up the number of available GPIO lines in Qualcomm QCS8300 and
     QCS615"

* tag 'pinctrl-v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
  pinctrl: freescale: Add support for imx943 pinctrl
  pinctrl: core: add devm_pinctrl_register_mappings()
  pinctrl: remove extern specifier for functions in machine.h
  pinctrl: mediatek: eint: Fix invalid pointer dereference for v1 platforms
  pinctrl: freescale: Enable driver if platform is enabled.
  pinctrl: freescale: Depend imx-scu driver on OF
  pinctrl: armada-37xx: propagate error from armada_37xx_pmx_set_by_name()
  pinctrl: armada-37xx: propagate error from armada_37xx_gpio_get_direction()
  pinctrl: armada-37xx: propagate error from armada_37xx_pmx_gpio_set_direction()
  pinctrl: armada-37xx: propagate error from armada_37xx_gpio_get()
  pinctrl: armada-37xx: propagate error from armada_37xx_gpio_direction_output()
  pinctrl: armada-37xx: set GPIO output value before setting direction
  pinctrl: armada-37xx: use correct OUTPUT_VAL register for GPIOs > 31
  pinctrl: meson: Drop unused aml_pctl_find_group_by_name()
  pinctrl: at91: Fix possible out-of-boundary access
  pinctrl: add stubs for OF-specific pinconf functions
  pinctrl: qcom: correct the ngpios entry for QCS8300
  pinctrl: qcom: correct the ngpios entry for QCS615
  dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
  dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
  ...
parents 9f32a03e 08dcbe30

Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml

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@@ -14,7 +14,12 @@ allOf: 


properties:

  compatible:

    const: amlogic,pinctrl-a4

    oneOf:

      - const: amlogic,pinctrl-a4

      - items:

          - enum:

              - amlogic,pinctrl-a5

          - const: amlogic,pinctrl-a4



  "#address-cells":

    const: 2

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx7ulp-iomuxc1.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX7ULP IOMUX Controller



description: |

  i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7

  ports and IOMUXC DDR for DDR interface.



  Note: This binding doc is only for the IOMUXC1 support in A7 Domain and it

  only supports generic pin config.



  Please refer to fsl,imx-pinctrl.txt in this directory for common binding

  part and usage.



maintainers:

  - Frank Li <Frank.Li@nxp.com>



properties:

  compatible:

    const: fsl,imx7ulp-iomuxc1



  reg:

    maxItems: 1



patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          Each entry consists of 5 integers which represents the mux

          and config setting for one pin. The first 4 integers

          <mux_conf_reg input_reg mux_mode input_val> are specified

          using a PIN_FUNC_ID macro, which can be found in

          imx7ulp-pinfunc.h in the device tree source folder.

          The last integer CONFIG is the pad setting value like

          pull-up on this pin.



          Please refer to i.MX7ULP Reference Manual for detailed

          CONFIG settings.

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        items:

          items:

            - description: |

                "mux_conf_reg" indicates the offset of mux register.

            - description: |

                "input_reg" indicates the offset of select input register.

            - description: |

                "mux_mode" indicates the mux value to be applied.

            - description: |

                "input_val" indicates the select input value to be applied.

            - description: |

                CONFIG bits definition:

                  PAD_CTL_OBE           (1 << 17)

                  PAD_CTL_IBE           (1 << 16)

                  PAD_CTL_LK            (1 << 16)

                  PAD_CTL_DSE_HI        (1 << 6)

                  PAD_CTL_DSE_STD       (0 << 6)

                  PAD_CTL_ODE           (1 << 5)

                  PAD_CTL_PUSH_PULL     (0 << 5)

                  PAD_CTL_SRE_SLOW      (1 << 2)

                  PAD_CTL_SRE_STD       (0 << 2)

                  PAD_CTL_PE            (1 << 0)



    required:

      - fsl,pins



    additionalProperties: false



required:

  - compatible

  - reg



allOf:

  - $ref: pinctrl.yaml#



unevaluatedProperties: false



examples:

  - |

    pinctrl@40ac0000 {

        compatible = "fsl,imx7ulp-iomuxc1";

        reg = <0x40ac0000 0x1000>;



        lpuart4grp {

            fsl,pins = <

                0x000c 0x0248 0x4 0x1 0x1

                0x0008 0x024c 0x4 0x1 0x1

            >;

        };

    };

Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt

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* Freescale i.MX7ULP IOMUX Controller



i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7

ports and IOMUXC DDR for DDR interface.



Note:

This binding doc is only for the IOMUXC1 support in A7 Domain and it only

supports generic pin config.



Please refer to fsl,imx-pinctrl.txt in this directory for common binding

part and usage.



Required properties:

- compatible:	"fsl,imx7ulp-iomuxc1".

- fsl,pins:	Each entry consists of 5 integers which represents the mux

		and config setting for one pin. The first 4 integers

		<mux_conf_reg input_reg mux_mode input_val> are specified

		using a PIN_FUNC_ID macro, which can be found in

		imx7ulp-pinfunc.h in the device tree source folder.

		The last integer CONFIG is the pad setting value like

		pull-up on this pin.



		Please refer to i.MX7ULP Reference Manual for detailed

		CONFIG settings.



CONFIG bits definition:

PAD_CTL_OBE		(1 << 17)

PAD_CTL_IBE		(1 << 16)

PAD_CTL_LK		(1 << 16)

PAD_CTL_DSE_HI		(1 << 6)

PAD_CTL_DSE_STD		(0 << 6)

PAD_CTL_ODE		(1 << 5)

PAD_CTL_PUSH_PULL	(0 << 5)

PAD_CTL_SRE_SLOW	(1 << 2)

PAD_CTL_SRE_STD		(0 << 2)

PAD_CTL_PE		(1 << 0)



Examples:

#include "imx7ulp-pinfunc.h"



/* Pin Controller Node */

iomuxc1: pinctrl@40ac0000 {

	compatible = "fsl,imx7ulp-iomuxc1";

	reg = <0x40ac0000 0x1000>;



	/* Pin Configuration Node */

	pinctrl_lpuart4: lpuart4grp {

		fsl,pins = <

			IMX7ULP_PAD_PTC3__LPUART4_RX	0x1

			IMX7ULP_PAD_PTC2__LPUART4_TX	0x1

		>;

	};

};

Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,vf610-iomuxc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale Vybrid VF610 IOMUX Controller



description:

  Please refer to fsl,imx-pinctrl.txt in this directory for common binding part

  and usage.



maintainers:

  - Frank Li <Frank.Li@nxp.com>



properties:

  compatible:

    const: fsl,vf610-iomuxc



  reg:

    maxItems: 1



patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          two integers array, represents a group of pins mux and config setting.

          The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a pin

          working on a specific function, CONFIG is the pad setting value such

          as pull-up, speed, ode for this pin. Please refer to Vybrid VF610

          datasheet for the valid pad config settings.

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        items:

          items:

            - description:

                PIN_FUN_ID refer to vf610-pinfunc.h in device tree source folder

                for all available PIN_FUNC_ID for Vybrid VF610.

            - description: |

                CONFIG bits definition is

                PAD_CTL_SPEED_LOW               (1 << 12)

                PAD_CTL_SPEED_MED               (2 << 12)

                PAD_CTL_SPEED_HIGH              (3 << 12)

                PAD_CTL_SRE_FAST                (1 << 11)

                PAD_CTL_SRE_SLOW                (0 << 11)

                PAD_CTL_ODE                     (1 << 10)

                PAD_CTL_HYS                     (1 << 9)

                PAD_CTL_DSE_DISABLE             (0 << 6)

                PAD_CTL_DSE_150ohm              (1 << 6)

                PAD_CTL_DSE_75ohm               (2 << 6)

                PAD_CTL_DSE_50ohm               (3 << 6)

                PAD_CTL_DSE_37ohm               (4 << 6)

                PAD_CTL_DSE_30ohm               (5 << 6)

                PAD_CTL_DSE_25ohm               (6 << 6)

                PAD_CTL_DSE_20ohm               (7 << 6)

                PAD_CTL_PUS_100K_DOWN           (0 << 4)

                PAD_CTL_PUS_47K_UP              (1 << 4)

                PAD_CTL_PUS_100K_UP             (2 << 4)

                PAD_CTL_PUS_22K_UP              (3 << 4)

                PAD_CTL_PKE                     (1 << 3)

                PAD_CTL_PUE                     (1 << 2)

                PAD_CTL_OBE_ENABLE              (1 << 1)

                PAD_CTL_IBE_ENABLE              (1 << 0)

                PAD_CTL_OBE_IBE_ENABLE          (3 << 0)



    required:

      - fsl,pins



    additionalProperties: false



required:

  - compatible

  - reg



allOf:

  - $ref: pinctrl.yaml#



unevaluatedProperties: false

Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt

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Freescale Vybrid VF610 IOMUX Controller



Please refer to fsl,imx-pinctrl.txt in this directory for common binding part

and usage.



Required properties:

- compatible: "fsl,vf610-iomuxc"

- fsl,pins: two integers array, represents a group of pins mux and config

  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is

  a pin working on a specific function, CONFIG is the pad setting value

  such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610

  datasheet for the valid pad config settings.



CONFIG bits definition:

PAD_CTL_SPEED_LOW		(1 << 12)

PAD_CTL_SPEED_MED		(2 << 12)

PAD_CTL_SPEED_HIGH		(3 << 12)

PAD_CTL_SRE_FAST		(1 << 11)

PAD_CTL_SRE_SLOW		(0 << 11)

PAD_CTL_ODE			(1 << 10)

PAD_CTL_HYS			(1 << 9)

PAD_CTL_DSE_DISABLE		(0 << 6)

PAD_CTL_DSE_150ohm		(1 << 6)

PAD_CTL_DSE_75ohm		(2 << 6)

PAD_CTL_DSE_50ohm		(3 << 6)

PAD_CTL_DSE_37ohm		(4 << 6)

PAD_CTL_DSE_30ohm		(5 << 6)

PAD_CTL_DSE_25ohm		(6 << 6)

PAD_CTL_DSE_20ohm		(7 << 6)

PAD_CTL_PUS_100K_DOWN		(0 << 4)

PAD_CTL_PUS_47K_UP		(1 << 4)

PAD_CTL_PUS_100K_UP		(2 << 4)

PAD_CTL_PUS_22K_UP		(3 << 4)

PAD_CTL_PKE			(1 << 3)

PAD_CTL_PUE			(1 << 2)

PAD_CTL_OBE_ENABLE		(1 << 1)

PAD_CTL_IBE_ENABLE		(1 << 0)

PAD_CTL_OBE_IBE_ENABLE		(3 << 0)



Please refer to vf610-pinfunc.h in device tree source folder

for all available PIN_FUNC_ID for Vybrid VF610.