Commit eb0e3f30 authored by Sascha Hauer's avatar Sascha Hauer Committed by Borislav Petkov (AMD)
Browse files

dt-bindings: arm: cpus: Add edac-enabled property 



Some ARM Cortex CPUs including A72 have Error Detection And Correction (EDAC)
support on their L1 and L2 caches. That functionality is in implementation
defined registers, so using it is not safe in virtualized environments or when
EL3 already uses these registers. Add a edac-enabled flag which can be
explicitly set when EDAC can be used.

  [ bp: Massage commit message. ]

Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarVijay Balakrishna <vijayb@linux.microsoft.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/1752714390-27389-3-git-send-email-vijayb@linux.microsoft.com
parent fb13ae06

Documentation/devicetree/bindings/arm/cpus.yaml

+17 −0
Original line number Diff line number Diff line
@@ -353,6 +353,12 @@ properties: 
    $ref: /schemas/types.yaml#/definitions/phandle

    description: Link to Mediatek Cache Coherent Interconnect



  edac-enabled:

    $ref: /schemas/types.yaml#/definitions/flag

    description:

      A72 CPUs support Error Detection And Correction (EDAC) on their L1 and

      L2 caches. This flag marks this function as usable.



  qcom,saw:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:
@@ -399,6 +405,17 @@ properties: 
allOf:

  - $ref: /schemas/cpu.yaml#

  - $ref: /schemas/opp/opp-v1.yaml#

  - if:

      not:

        properties:

          compatible:

            contains:

              const: arm,cortex-a72

    then:

      # Allow edac-enabled only for Cortex A72

      properties:

        edac-enabled: false



  - if:

      # If the enable-method property contains one of those values

      properties: