Commit eb15a5d1 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx11: dump full CP packet header FIFOs 



In dev core dump, dump the full header fifo for
each queue. Each FIFO has 8 entries.

Reviewed-by: default avatarPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 867cf768

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+49 −10
Original line number Diff line number Diff line
@@ -177,9 +177,13 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),

	/* cp header registers */

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	/* SE status registers */

	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
@@ -230,7 +234,16 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)

	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),

	/* cp header registers */

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

};



static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = {
@@ -259,7 +272,24 @@ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),

	/* cp header registers */

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

};



static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
@@ -6892,6 +6922,11 @@ static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printe 
			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {

				drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);

				for (reg = 0; reg < reg_count; reg++) {

					if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP)

						drm_printf(p, "%-50s \t 0x%08x\n",

							   "regCP_MEC_ME2_HEADER_DUMP",

							   adev->gfx.ip_dump_compute_queues[index + reg]);

					else

						drm_printf(p, "%-50s \t 0x%08x\n",

							   gc_cp_reg_list_11[reg].reg_name,

							   adev->gfx.ip_dump_compute_queues[index + reg]);
@@ -6954,6 +6989,10 @@ static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block) 
				/* ME0 is for GFX so start from 1 for CP */

				soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);

				for (reg = 0; reg < reg_count; reg++) {

					if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP)

					adev->gfx.ip_dump_compute_queues[index + reg] =

						RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC_ME2_HEADER_DUMP));

					else

						adev->gfx.ip_dump_compute_queues[index + reg] =

							RREG32(SOC15_REG_ENTRY_OFFSET(

								       gc_cp_reg_list_11[reg]));