Commit eb1c7c08 authored by Ahmed S. Darwish's avatar Ahmed S. Darwish Committed by Ingo Molnar
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x86/cacheinfo: Rename 'struct _cpuid4_info_regs' to 'struct _cpuid4_info' 



Parent commits decoupled amd_northbridge from _cpuid4_info_regs, moved
AMD L3 northbridge cache_disable_0/1 sysfs code to its own file, and
splitted AMD vs. Intel leaf 0x4 handling into:

    amd_fill_cpuid4_info()
    intel_fill_cpuid4_info()
    fill_cpuid4_info()

After doing all that, the "_cpuid4_info_regs" name becomes a mouthful.
It is also not totally accurate, as the structure holds cpuid4 derived
information like cache node ID and size -- not just regs.

Rename struct _cpuid4_info_regs to _cpuid4_info.  That new name also
better matches the AMD/Intel leaf 0x4 functions mentioned above.

Signed-off-by: default avatarAhmed S. Darwish <darwi@linutronix.de>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20250324133324.23458-17-darwi@linutronix.de
parent 2d56cc87

arch/x86/kernel/cpu/cacheinfo.c

+11 −11
Original line number Diff line number Diff line
@@ -159,7 +159,7 @@ union _cpuid4_leaf_ecx { 
	u32 full;

};



struct _cpuid4_info_regs {

struct _cpuid4_info {

	union _cpuid4_leaf_eax eax;

	union _cpuid4_leaf_ebx ebx;

	union _cpuid4_leaf_ecx ecx;
@@ -295,7 +295,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_leaf_eax *eax, 
		(ebx->split.ways_of_associativity + 1) - 1;

}



static int cpuid4_info_fill_done(struct _cpuid4_info_regs *id4, union _cpuid4_leaf_eax eax,

static int cpuid4_info_fill_done(struct _cpuid4_info *id4, union _cpuid4_leaf_eax eax,

				 union _cpuid4_leaf_ebx ebx, union _cpuid4_leaf_ecx ecx)

{

	if (eax.split.type == CTYPE_NULL)
@@ -312,7 +312,7 @@ static int cpuid4_info_fill_done(struct _cpuid4_info_regs *id4, union _cpuid4_le 
	return 0;

}



static int amd_fill_cpuid4_info(int index, struct _cpuid4_info_regs *id4)

static int amd_fill_cpuid4_info(int index, struct _cpuid4_info *id4)

{

	union _cpuid4_leaf_eax eax;

	union _cpuid4_leaf_ebx ebx;
@@ -327,7 +327,7 @@ static int amd_fill_cpuid4_info(int index, struct _cpuid4_info_regs *id4) 
	return cpuid4_info_fill_done(id4, eax, ebx, ecx);

}



static int intel_fill_cpuid4_info(int index, struct _cpuid4_info_regs *id4)

static int intel_fill_cpuid4_info(int index, struct _cpuid4_info *id4)

{

	union _cpuid4_leaf_eax eax;

	union _cpuid4_leaf_ebx ebx;
@@ -339,7 +339,7 @@ static int intel_fill_cpuid4_info(int index, struct _cpuid4_info_regs *id4) 
	return cpuid4_info_fill_done(id4, eax, ebx, ecx);

}



static int fill_cpuid4_info(int index, struct _cpuid4_info_regs *id4)

static int fill_cpuid4_info(int index, struct _cpuid4_info *id4)

{

	u8 cpu_vendor = boot_cpu_data.x86_vendor;
@@ -476,7 +476,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) 
		 * parameters cpuid leaf to find the cache details

		 */

		for (i = 0; i < ci->num_leaves; i++) {

			struct _cpuid4_info_regs id4 = {};

			struct _cpuid4_info id4 = {};

			int retval;



			retval = intel_fill_cpuid4_info(i, &id4);
@@ -563,7 +563,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) 
}



static int __cache_amd_cpumap_setup(unsigned int cpu, int index,

				    const struct _cpuid4_info_regs *id4)

				    const struct _cpuid4_info *id4)

{

	struct cpu_cacheinfo *this_cpu_ci;

	struct cacheinfo *ci;
@@ -620,7 +620,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, int index, 
}



static void __cache_cpumap_setup(unsigned int cpu, int index,

				 const struct _cpuid4_info_regs *id4)

				 const struct _cpuid4_info *id4)

{

	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);

	struct cacheinfo *ci, *sibling_ci;
@@ -655,7 +655,7 @@ static void __cache_cpumap_setup(unsigned int cpu, int index, 
		}

}



static void ci_info_init(struct cacheinfo *ci, const struct _cpuid4_info_regs *id4,

static void ci_info_init(struct cacheinfo *ci, const struct _cpuid4_info *id4,

			 struct amd_northbridge *nb)

{

	ci->id				= id4->id;
@@ -686,7 +686,7 @@ int init_cache_level(unsigned int cpu) 
 * ECX as cache index. Then right shift apicid by the number's order to get

 * cache id for this cache node.

 */

static void get_cache_id(int cpu, struct _cpuid4_info_regs *id4)

static void get_cache_id(int cpu, struct _cpuid4_info *id4)

{

	struct cpuinfo_x86 *c = &cpu_data(cpu);

	unsigned long num_threads_sharing;
@@ -702,8 +702,8 @@ int populate_cache_leaves(unsigned int cpu) 
	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);

	struct cacheinfo *ci = this_cpu_ci->info_list;

	u8 cpu_vendor = boot_cpu_data.x86_vendor;

	struct _cpuid4_info_regs id4 = {};

	struct amd_northbridge *nb = NULL;

	struct _cpuid4_info id4 = {};

	int idx, ret;



	for (idx = 0; idx < this_cpu_ci->num_leaves; idx++) {