Commit eb30d838 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Catalin Marinas
Browse files

arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges 



Errata ARM64_ERRATUM_[2119858|2224489] also affect some Cortex-X2 ranges as
well. Lets update these errata definition and detection to accommodate all
new Cortex-X2 based cpu MIDR ranges.

Cc: Will Deacon <will@kernel.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1642994138-25887-3-git-send-email-anshuman.khandual@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 72bb9dcb

Documentation/arm64/silicon-errata.rst

+4 −0
Original line number Diff line number Diff line
@@ -98,6 +98,10 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

arch/arm64/Kconfig

+6 −6
Original line number Diff line number Diff line
@@ -671,14 +671,14 @@ config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 
	bool



config ARM64_ERRATUM_2119858

	bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"

	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"

	default y

	depends on CORESIGHT_TRBE

	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	help

	  This option adds the workaround for ARM Cortex-A710 erratum 2119858.

	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.



	  Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace

	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace

	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in

	  the event of a WRAP event.
@@ -761,14 +761,14 @@ config ARM64_ERRATUM_2253138 
	  If unsure, say Y.



config ARM64_ERRATUM_2224489

	bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"

	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"

	depends on CORESIGHT_TRBE

	default y

	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

	help

	  This option adds the workaround for ARM Cortex-A710 erratum 2224489.

	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.



	  Affected Cortex-A710 cores might write to an out-of-range address, not reserved

	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved

	  for TRBE. Under some conditions, the TRBE might generate a write to the next

	  virtually addressed page following the last page of the TRBE address space

	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.

arch/arm64/kernel/cpu_errata.c

+2 −0
Original line number Diff line number Diff line
@@ -347,6 +347,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 
#endif

#ifdef CONFIG_ARM64_ERRATUM_2119858

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),

#endif

	{},

};
@@ -371,6 +372,7 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { 
#endif

#ifdef CONFIG_ARM64_ERRATUM_2224489

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

	MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),

#endif

	{},

};