Commit eb3765aa authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips-fixes_7.0_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS fixes from Thomas Bogendoerfer:

 - Fix TLB uniquification for systems with TLB not initialised by
   firmware

 - Fix allocation in TLB uniquification

 - Fix SiByte cache initialisation

 - Check uart parameters from firmware on Loongson64 systems

 - Fix clock id mismatch for Ralink SoCs

 - Fix GCC version check for __mutli3 workaround

* tag 'mips-fixes_7.0_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  mips: mm: Allocate tlb_vpn array atomically
  MIPS: mm: Rewrite TLB uniquification for the hidden bit feature
  MIPS: mm: Suppress TLB uniquification on EHINV hardware
  MIPS: Always record SEGBITS in cpu_data.vmbits
  MIPS: Fix the GCC version check for `__multi3' workaround
  MIPS: SiByte: Bring back cache initialisation
  mips: ralink: update CPU clock index
  MIPS: Loongson64: env: Check UARTs passed by LEFI cautiously
parents 1791c390 01cc50ea

arch/mips/include/asm/cpu-features.h

+0 −1
Original line number Diff line number Diff line
@@ -484,7 +484,6 @@ 
# endif

# ifndef cpu_vmbits

# define cpu_vmbits cpu_data[0].vmbits

# define __NEED_VMBITS_PROBE

# endif

#endif

arch/mips/include/asm/cpu-info.h

+0 −2
Original line number Diff line number Diff line
@@ -80,9 +80,7 @@ struct cpuinfo_mips { 
	int			srsets; /* Shadow register sets */

	int			package;/* physical package number */

	unsigned int		globalnumber;

#ifdef CONFIG_64BIT

	int			vmbits; /* Virtual memory size in bits */

#endif

	void			*data;	/* Additional data */

	unsigned int		watch_reg_count;   /* Number that exist */

	unsigned int		watch_reg_use_cnt; /* Usable by ptrace */

arch/mips/include/asm/mipsregs.h

+2 −0
Original line number Diff line number Diff line
@@ -1871,6 +1871,8 @@ do { \ 


#define read_c0_entryhi()	__read_ulong_c0_register($10, 0)

#define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)

#define read_c0_entryhi_64()	__read_64bit_c0_register($10, 0)

#define write_c0_entryhi_64(val) __write_64bit_c0_register($10, 0, val)



#define read_c0_guestctl1()	__read_32bit_c0_register($10, 4)

#define write_c0_guestctl1(val)	__write_32bit_c0_register($10, 4, val)

arch/mips/kernel/cpu-probe.c

+8 −5
Original line number Diff line number Diff line
@@ -210,11 +210,14 @@ static inline void set_elf_base_platform(const char *plat) 


static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)

{

#ifdef __NEED_VMBITS_PROBE

	write_c0_entryhi(0x3fffffffffffe000ULL);

	int vmbits = 31;



	if (cpu_has_64bits) {

		write_c0_entryhi_64(0x3fffffffffffe000ULL);

		back_to_back_c0_hazard();

	c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);

#endif

		vmbits = fls64(read_c0_entryhi_64() & 0x3fffffffffffe000ULL);

	}

	c->vmbits = vmbits;

}



static void set_isa(struct cpuinfo_mips *c, unsigned int isa)

arch/mips/kernel/cpu-r3k-probe.c

+2 −0
Original line number Diff line number Diff line
@@ -137,6 +137,8 @@ void cpu_probe(void) 
	else

		cpu_set_nofpu_opts(c);



	c->vmbits = 31;



	reserve_exception_space(0, 0x400);

}