Commit eb43534e authored by Conor Dooley's avatar Conor Dooley Committed by Claudiu Beznea
Browse files

dt-bindings: clk: microchip: mpfs: remove first reg region 



The first reg region in this binding is not exclusively for clocks, as
evidenced by the dual role of this device as a reset controller at
present. The first region is however better described by a simple-mfd
syscon, but this would have require a significant re-write of the
devicetree for the platform, so the easy way out was chosen when reset
support was first introduced. The region doesn't just contain clock and
reset registers, it also contains pinctrl and interrupt controller
functionality, so drop the region from the clock binding so that it can
be described instead by a simple-mfd syscon rather than propagate this
incorrect description of the hardware to the new pic64gx SoC.

Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20251029-unwatched-family-e47cb29ea815@spud


Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@tuxon.dev>
parent 3a866087

Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml

+22 −14
Original line number Diff line number Diff line
@@ -22,7 +22,8 @@ properties: 
    const: microchip,mpfs-clkcfg



  reg:

    items:

    oneOf:

      - items:

          - description: |

              clock config registers:

              These registers contain enable, reset & divider tables for the, cpu,
@@ -32,6 +33,12 @@ properties: 
              mss pll dri registers:

              Block of registers responsible for dynamic reconfiguration of the mss

              pll

        deprecated: true

      - items:

          - description: |

              mss pll dri registers:

              Block of registers responsible for dynamic reconfiguration of the mss

              pll



  clocks:

    maxItems: 1
@@ -69,11 +76,12 @@ examples: 
  - |

    #include <dt-bindings/clock/microchip,mpfs-clock.h>

    soc {

            #address-cells = <2>;

            #size-cells = <2>;

            clkcfg: clock-controller@20002000 {

            #address-cells = <1>;

            #size-cells = <1>;



            clkcfg: clock-controller@3E001000 {

                compatible = "microchip,mpfs-clkcfg";

                reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;

                reg = <0x3E001000 0x1000>;

                clocks = <&ref>;

                #clock-cells = <1>;

        };