Commit eb687212 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Dinh Nguyen
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arm64: dts: socfpga: agilex: move FPGA region out of soc node 



The "soc" node is supposed to have only MMIO children, so move the FPGA
region node to top level to fix dtc W=1 warnings like:

  socfpga_agilex.dtsi:141.20-146.5: Warning (simple_bus_reg): /soc@0/base_fpga_region: missing or empty reg/ranges property

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 5c7c75b9

arch/arm64/boot/dts/intel/socfpga_agilex.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -60,6 +60,13 @@ cpu3: cpu@3 { 
		};

	};



	fpga-region {

		compatible = "fpga-region";

		#address-cells = <0x2>;

		#size-cells = <0x2>;

		fpga-mgr = <&fpga_mgr>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
@@ -138,13 +145,6 @@ soc { 
		interrupt-parent = <&intc>;

		ranges = <0 0 0 0xffffffff>;



		base_fpga_region {

			#address-cells = <0x2>;

			#size-cells = <0x2>;

			compatible = "fpga-region";

			fpga-mgr = <&fpga_mgr>;

		};



		clkmgr: clock-controller@ffd10000 {

			compatible = "intel,agilex-clkmgr";

			reg = <0xffd10000 0x1000>;