Commit eb7205b7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2024-09-03' of... 

Merge tag 'drm-intel-next-2024-09-03' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

- Fix probe on 'nomodeset and deprecate i915.modeset=0 (Jani)
- Update new entries in VBT BDB block definitions (Dnyaneshwar)
- Fix clang build (Andy Shevchenko)
- More clean up on drvdata usage in display code (Jani)
- Increase fastwake DP sync pulse count as a quirk (Jouni)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZtcqaxYKgA5F7BXT@intel.com
parents e066e9aa 963ed4ef

drivers/gpu/drm/i915/display/g4x_dp.c

+82 −70
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ void g4x_dp_set_clock(struct intel_encoder *encoder, 
static void intel_dp_prepare(struct intel_encoder *encoder,

			     const struct intel_crtc_state *pipe_config)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	enum port port = encoder->port;
@@ -118,7 +119,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 
	/* Preserve the BIOS-computed detected bit. This is

	 * supposed to be read-only.

	 */

	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;

	intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;



	/* Handle DP bits in common between all three register formats */

	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
@@ -140,7 +141,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 
	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {

		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;



		intel_de_rmw(dev_priv, TRANS_DP_CTL(crtc->pipe),

		intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),

			     TRANS_DP_ENH_FRAMING,

			     pipe_config->enhanced_framing ?

			     TRANS_DP_ENH_FRAMING : 0);
@@ -166,9 +167,10 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 


static void assert_dp_port(struct intel_dp *intel_dp, bool state)

{

	struct intel_display *display = to_intel_display(intel_dp);

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);

	bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;

	bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;



	I915_STATE_WARN(dev_priv, cur_state != state,

			"[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
@@ -179,7 +181,8 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state) 


static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)

{

	bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;

	struct intel_display *display = &dev_priv->display;

	bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;



	I915_STATE_WARN(dev_priv, cur_state != state,

			"eDP PLL state assertion failure (expected %s, current %s)\n",
@@ -191,6 +194,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 
static void ilk_edp_pll_on(struct intel_dp *intel_dp,

			   const struct intel_crtc_state *pipe_config)

{

	struct intel_display *display = to_intel_display(intel_dp);

	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -198,7 +202,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, 
	assert_dp_port_disabled(intel_dp);

	assert_edp_pll_disabled(dev_priv);



	drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",

	drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",

		    pipe_config->port_clock);



	intel_dp->DP &= ~DP_PLL_FREQ_MASK;
@@ -208,8 +212,8 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, 
	else

		intel_dp->DP |= DP_PLL_FREQ_270MHZ;



	intel_de_write(dev_priv, DP_A, intel_dp->DP);

	intel_de_posting_read(dev_priv, DP_A);

	intel_de_write(display, DP_A, intel_dp->DP);

	intel_de_posting_read(display, DP_A);

	udelay(500);



	/*
@@ -223,14 +227,15 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, 


	intel_dp->DP |= DP_PLL_ENABLE;



	intel_de_write(dev_priv, DP_A, intel_dp->DP);

	intel_de_posting_read(dev_priv, DP_A);

	intel_de_write(display, DP_A, intel_dp->DP);

	intel_de_posting_read(display, DP_A);

	udelay(200);

}



static void ilk_edp_pll_off(struct intel_dp *intel_dp,

			    const struct intel_crtc_state *old_crtc_state)

{

	struct intel_display *display = to_intel_display(intel_dp);

	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -238,22 +243,23 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp, 
	assert_dp_port_disabled(intel_dp);

	assert_edp_pll_enabled(dev_priv);



	drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");

	drm_dbg_kms(display->drm, "disabling eDP PLL\n");



	intel_dp->DP &= ~DP_PLL_ENABLE;



	intel_de_write(dev_priv, DP_A, intel_dp->DP);

	intel_de_posting_read(dev_priv, DP_A);

	intel_de_write(display, DP_A, intel_dp->DP);

	intel_de_posting_read(display, DP_A);

	udelay(200);

}



static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,

				 enum port port, enum pipe *pipe)

{

	struct intel_display *display = &dev_priv->display;

	enum pipe p;



	for_each_pipe(dev_priv, p) {

		u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));

	for_each_pipe(display, p) {

		u32 val = intel_de_read(display, TRANS_DP_CTL(p));



		if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {

			*pipe = p;
@@ -261,7 +267,7 @@ static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, 
		}

	}



	drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",

	drm_dbg_kms(display->drm, "No pipe for DP port %c found\n",

		    port_name(port));



	/* must initialize pipe to something for the asserts */
@@ -274,10 +280,11 @@ bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, 
			 i915_reg_t dp_reg, enum port port,

			 enum pipe *pipe)

{

	struct intel_display *display = &dev_priv->display;

	bool ret;

	u32 val;



	val = intel_de_read(dev_priv, dp_reg);

	val = intel_de_read(display, dp_reg);



	ret = val & DP_PORT_EN;
@@ -333,6 +340,7 @@ static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state) 
static void intel_dp_get_config(struct intel_encoder *encoder,

				struct intel_crtc_state *pipe_config)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u32 tmp, flags = 0;
@@ -344,12 +352,12 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 
	else

		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);



	tmp = intel_de_read(dev_priv, intel_dp->output_reg);

	tmp = intel_de_read(display, intel_dp->output_reg);



	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;



	if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {

		u32 trans_dp = intel_de_read(dev_priv,

		u32 trans_dp = intel_de_read(display,

					     TRANS_DP_CTL(crtc->pipe));



		if (trans_dp & TRANS_DP_ENH_FRAMING)
@@ -390,7 +398,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 
	g4x_dp_get_m_n(pipe_config);



	if (port == PORT_A) {

		if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)

		if ((intel_de_read(display, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)

			pipe_config->port_clock = 162000;

		else

			pipe_config->port_clock = 270000;
@@ -410,17 +418,18 @@ static void 
intel_dp_link_down(struct intel_encoder *encoder,

		   const struct intel_crtc_state *old_crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);

	enum port port = encoder->port;



	if (drm_WARN_ON(&dev_priv->drm,

			(intel_de_read(dev_priv, intel_dp->output_reg) &

	if (drm_WARN_ON(display->drm,

			(intel_de_read(display, intel_dp->output_reg) &

			 DP_PORT_EN) == 0))

		return;



	drm_dbg_kms(&dev_priv->drm, "\n");

	drm_dbg_kms(display->drm, "\n");



	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||

	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
@@ -430,12 +439,12 @@ intel_dp_link_down(struct intel_encoder *encoder, 
		intel_dp->DP &= ~DP_LINK_TRAIN_MASK;

		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;

	}

	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(dev_priv, intel_dp->output_reg);

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);



	intel_dp->DP &= ~DP_PORT_EN;

	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(dev_priv, intel_dp->output_reg);

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);



	/*

	 * HW workaround for IBX, we need to move the port
@@ -454,12 +463,12 @@ intel_dp_link_down(struct intel_encoder *encoder, 
		intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);

		intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |

			DP_LINK_TRAIN_PAT_1;

		intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

		intel_de_posting_read(dev_priv, intel_dp->output_reg);

		intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

		intel_de_posting_read(display, intel_dp->output_reg);



		intel_dp->DP &= ~DP_PORT_EN;

		intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

		intel_de_posting_read(dev_priv, intel_dp->output_reg);

		intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

		intel_de_posting_read(display, intel_dp->output_reg);



		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);

		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
@@ -480,7 +489,7 @@ static void g4x_dp_audio_enable(struct intel_encoder *encoder, 
				const struct intel_crtc_state *crtc_state,

				const struct drm_connector_state *conn_state)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	struct intel_display *display = to_intel_display(encoder);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



	if (!crtc_state->has_audio)
@@ -488,7 +497,7 @@ static void g4x_dp_audio_enable(struct intel_encoder *encoder, 


	/* Enable audio presence detect */

	intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;

	intel_de_write(i915, intel_dp->output_reg, intel_dp->DP);

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);



	intel_audio_codec_enable(encoder, crtc_state, conn_state);

}
@@ -497,7 +506,7 @@ static void g4x_dp_audio_disable(struct intel_encoder *encoder, 
				 const struct intel_crtc_state *old_crtc_state,

				 const struct drm_connector_state *old_conn_state)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	struct intel_display *display = to_intel_display(encoder);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



	if (!old_crtc_state->has_audio)
@@ -507,7 +516,7 @@ static void g4x_dp_audio_disable(struct intel_encoder *encoder, 


	/* Disable audio presence detect */

	intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE;

	intel_de_write(i915, intel_dp->output_reg, intel_dp->DP);

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

}



static void intel_disable_dp(struct intel_atomic_state *state,
@@ -596,7 +605,7 @@ cpt_set_link_train(struct intel_dp *intel_dp, 
		   const struct intel_crtc_state *crtc_state,

		   u8 dp_train_pat)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);



	intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
@@ -615,8 +624,8 @@ cpt_set_link_train(struct intel_dp *intel_dp, 
		return;

	}



	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(dev_priv, intel_dp->output_reg);

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);

}



static void
@@ -624,7 +633,7 @@ g4x_set_link_train(struct intel_dp *intel_dp, 
		   const struct intel_crtc_state *crtc_state,

		   u8 dp_train_pat)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);



	intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
@@ -643,14 +652,14 @@ g4x_set_link_train(struct intel_dp *intel_dp, 
		return;

	}



	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(dev_priv, intel_dp->output_reg);

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);

}



static void intel_dp_enable_port(struct intel_dp *intel_dp,

				 const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);



	/* enable with pattern 1 (as per spec) */
@@ -665,8 +674,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp, 
	 */

	intel_dp->DP |= DP_PORT_EN;



	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(dev_priv, intel_dp->output_reg);

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);

}



static void intel_enable_dp(struct intel_atomic_state *state,
@@ -674,12 +683,13 @@ static void intel_enable_dp(struct intel_atomic_state *state, 
			    const struct intel_crtc_state *pipe_config,

			    const struct drm_connector_state *conn_state)

{

	struct intel_display *display = to_intel_display(state);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);

	u32 dp_reg = intel_de_read(display, intel_dp->output_reg);

	intel_wakeref_t wakeref;



	if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))

	if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))

		return;



	with_intel_pps_lock(intel_dp, wakeref) {
@@ -1026,21 +1036,21 @@ static void 
g4x_set_signal_levels(struct intel_encoder *encoder,

		      const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_display *display = to_intel_display(encoder);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u8 train_set = intel_dp->train_set[0];

	u32 signal_levels;



	signal_levels = g4x_signal_levels(train_set);



	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",

	drm_dbg_kms(display->drm, "Using signal levels %08x\n",

		    signal_levels);



	intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);

	intel_dp->DP |= signal_levels;



	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(dev_priv, intel_dp->output_reg);

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);

}



/* SNB CPU eDP voltage swing and pre-emphasis control */
@@ -1074,21 +1084,21 @@ static void 
snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,

			      const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_display *display = to_intel_display(encoder);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u8 train_set = intel_dp->train_set[0];

	u32 signal_levels;



	signal_levels = snb_cpu_edp_signal_levels(train_set);



	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",

	drm_dbg_kms(display->drm, "Using signal levels %08x\n",

		    signal_levels);



	intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;

	intel_dp->DP |= signal_levels;



	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(dev_priv, intel_dp->output_reg);

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);

}



/* IVB CPU eDP voltage swing and pre-emphasis control */
@@ -1126,21 +1136,21 @@ static void 
ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,

			      const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_display *display = to_intel_display(encoder);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u8 train_set = intel_dp->train_set[0];

	u32 signal_levels;



	signal_levels = ivb_cpu_edp_signal_levels(train_set);



	drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",

	drm_dbg_kms(display->drm, "Using signal levels %08x\n",

		    signal_levels);



	intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;

	intel_dp->DP |= signal_levels;



	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(dev_priv, intel_dp->output_reg);

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);

}



/*
@@ -1185,15 +1195,15 @@ intel_dp_hotplug(struct intel_encoder *encoder, 


static bool ibx_digital_port_connected(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];

	struct intel_display *display = to_intel_display(encoder);

	u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];



	return intel_de_read(dev_priv, SDEISR) & bit;

	return intel_de_read(display, SDEISR) & bit;

}



static bool g4x_digital_port_connected(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_display *display = to_intel_display(encoder);

	u32 bit;



	switch (encoder->hpd_pin) {
@@ -1211,15 +1221,15 @@ static bool g4x_digital_port_connected(struct intel_encoder *encoder) 
		return false;

	}



	return intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv)) & bit;

	return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;

}



static bool ilk_digital_port_connected(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];

	struct intel_display *display = to_intel_display(encoder);

	u32 bit = display->hotplug.hpd[encoder->hpd_pin];



	return intel_de_read(dev_priv, DEISR) & bit;

	return intel_de_read(display, DEISR) & bit;

}



static void g4x_dp_suspend_complete(struct intel_encoder *encoder)
@@ -1241,7 +1251,8 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 


enum pipe vlv_active_pipe(struct intel_dp *intel_dp)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	enum pipe pipe;
@@ -1254,10 +1265,11 @@ enum pipe vlv_active_pipe(struct intel_dp *intel_dp) 


static void intel_dp_encoder_reset(struct drm_encoder *encoder)

{

	struct intel_display *display = to_intel_display(encoder->dev);

	struct drm_i915_private *dev_priv = to_i915(encoder->dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));



	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);

	intel_dp->DP = intel_de_read(display, intel_dp->output_reg);



	intel_dp->reset_link_params = true;
@@ -1293,7 +1305,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, 


	/* FIXME bail? */

	if (!devdata)

		drm_dbg_kms(&dev_priv->drm, "No VBT child device for DP-%c\n",

		drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",

			    port_name(port));



	dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
@@ -1313,7 +1325,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, 


	mutex_init(&dig_port->hdcp_mutex);



	if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,

	if (drm_encoder_init(display->drm, &intel_encoder->base,

			     &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,

			     "DP %c", port_name(port)))

		goto err_encoder_init;
@@ -1397,7 +1409,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, 


	dig_port->hpd_pulse = intel_dp_hpd_pulse;



	if (HAS_GMCH(dev_priv)) {

	if (HAS_GMCH(display)) {

		dig_port->connected = g4x_digital_port_connected;

	} else {

		if (port == PORT_A)

drivers/gpu/drm/i915/display/intel_alpm.c

+1 −1
Original line number Diff line number Diff line
@@ -228,7 +228,7 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp, 
	int tfw_exit_latency = 20; /* eDP spec */

	int phy_wake = 4;	   /* eDP spec */

	int preamble = 8;	   /* eDP spec */

	int precharge = intel_dp_aux_fw_sync_len() - preamble;

	int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble;

	u8 max_wake_lines;



	io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) +

drivers/gpu/drm/i915/display/intel_audio.c

+21 −13
Original line number Diff line number Diff line
@@ -980,7 +980,8 @@ static void glk_force_audio_cdclk(struct drm_i915_private *i915, 


static unsigned long i915_audio_component_get_power(struct device *kdev)

{

	struct drm_i915_private *i915 = kdev_to_i915(kdev);

	struct intel_display *display = to_intel_display(kdev);

	struct drm_i915_private *i915 = to_i915(display->drm);

	intel_wakeref_t ret;



	/* Catch potential impedance mismatches before they occur! */
@@ -1012,7 +1013,8 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) 
static void i915_audio_component_put_power(struct device *kdev,

					   unsigned long cookie)

{

	struct drm_i915_private *i915 = kdev_to_i915(kdev);

	struct intel_display *display = to_intel_display(kdev);

	struct drm_i915_private *i915 = to_i915(display->drm);



	/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */

	if (--i915->display.audio.power_refcount == 0)
@@ -1025,7 +1027,8 @@ static void i915_audio_component_put_power(struct device *kdev, 
static void i915_audio_component_codec_wake_override(struct device *kdev,

						     bool enable)

{

	struct drm_i915_private *i915 = kdev_to_i915(kdev);

	struct intel_display *display = to_intel_display(kdev);

	struct drm_i915_private *i915 = to_i915(display->drm);

	unsigned long cookie;



	if (DISPLAY_VER(i915) < 9)
@@ -1053,7 +1056,8 @@ static void i915_audio_component_codec_wake_override(struct device *kdev, 
/* Get CDCLK in kHz  */

static int i915_audio_component_get_cdclk_freq(struct device *kdev)

{

	struct drm_i915_private *i915 = kdev_to_i915(kdev);

	struct intel_display *display = to_intel_display(kdev);

	struct drm_i915_private *i915 = to_i915(display->drm);



	if (drm_WARN_ON_ONCE(&i915->drm, !HAS_DDI(i915)))

		return -ENODEV;
@@ -1112,7 +1116,8 @@ static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915, 
static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,

						int cpu_transcoder, int rate)

{

	struct drm_i915_private *i915 = kdev_to_i915(kdev);

	struct intel_display *display = to_intel_display(kdev);

	struct drm_i915_private *i915 = to_i915(display->drm);

	struct i915_audio_component *acomp = i915->display.audio.component;

	const struct intel_audio_state *audio_state;

	struct intel_encoder *encoder;
@@ -1154,7 +1159,8 @@ static int i915_audio_component_get_eld(struct device *kdev, int port, 
					int cpu_transcoder, bool *enabled,

					unsigned char *buf, int max_bytes)

{

	struct drm_i915_private *i915 = kdev_to_i915(kdev);

	struct intel_display *display = to_intel_display(kdev);

	struct drm_i915_private *i915 = to_i915(display->drm);

	const struct intel_audio_state *audio_state;

	int ret = 0;
@@ -1189,24 +1195,25 @@ static const struct drm_audio_component_ops i915_audio_component_ops = { 
	.get_eld	= i915_audio_component_get_eld,

};



static int i915_audio_component_bind(struct device *i915_kdev,

static int i915_audio_component_bind(struct device *drv_kdev,

				     struct device *hda_kdev, void *data)

{

	struct intel_display *display = to_intel_display(drv_kdev);

	struct drm_i915_private *i915 = to_i915(display->drm);

	struct i915_audio_component *acomp = data;

	struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);

	int i;



	if (drm_WARN_ON(&i915->drm, acomp->base.ops || acomp->base.dev))

		return -EEXIST;



	if (drm_WARN_ON(&i915->drm,

			!device_link_add(hda_kdev, i915_kdev,

			!device_link_add(hda_kdev, drv_kdev,

					 DL_FLAG_STATELESS)))

		return -ENOMEM;



	drm_modeset_lock_all(&i915->drm);

	acomp->base.ops = &i915_audio_component_ops;

	acomp->base.dev = i915_kdev;

	acomp->base.dev = drv_kdev;

	BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);

	for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)

		acomp->aud_sample_rate[i] = 0;
@@ -1216,11 +1223,12 @@ static int i915_audio_component_bind(struct device *i915_kdev, 
	return 0;

}



static void i915_audio_component_unbind(struct device *i915_kdev,

static void i915_audio_component_unbind(struct device *drv_kdev,

					struct device *hda_kdev, void *data)

{

	struct intel_display *display = to_intel_display(drv_kdev);

	struct drm_i915_private *i915 = to_i915(display->drm);

	struct i915_audio_component *acomp = data;

	struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);



	drm_modeset_lock_all(&i915->drm);

	acomp->base.ops = NULL;
@@ -1228,7 +1236,7 @@ static void i915_audio_component_unbind(struct device *i915_kdev, 
	i915->display.audio.component = NULL;

	drm_modeset_unlock_all(&i915->drm);



	device_link_remove(hda_kdev, i915_kdev);

	device_link_remove(hda_kdev, drv_kdev);



	if (i915->display.audio.power_refcount)

		drm_err(&i915->drm, "audio power refcount %d after unbind\n",

drivers/gpu/drm/i915/display/intel_ddi.c

+7 −7
Original line number Diff line number Diff line
@@ -1400,7 +1400,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 
static int translate_signal_level(struct intel_dp *intel_dp,

				  u8 signal_levels)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);

	int i;



	for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
@@ -1408,7 +1408,7 @@ static int translate_signal_level(struct intel_dp *intel_dp, 
			return i;

	}



	drm_WARN(&i915->drm, 1,

	drm_WARN(display->drm, 1,

		 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",

		 signal_levels);
@@ -2211,14 +2211,14 @@ static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel 
							  const struct intel_crtc_state *crtc_state,

							  bool enable)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);



	if (!crtc_state->vrr.enable)

		return;



	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,

			       enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)

		drm_dbg_kms(&i915->drm,

		drm_dbg_kms(display->drm,

			    "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",

			    str_enable_disable(enable));

}
@@ -2227,20 +2227,20 @@ static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 
					const struct intel_crtc_state *crtc_state,

					bool enable)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct intel_display *display = to_intel_display(intel_dp);



	if (!crtc_state->fec_enable)

		return;



	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,

			       enable ? DP_FEC_READY : 0) <= 0)

		drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n",

		drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n",

			    enable ? "enabled" : "disabled");



	if (enable &&

	    drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,

			       DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0)

		drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n");

		drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n");

}



static int read_fec_detected_status(struct drm_dp_aux *aux)

drivers/gpu/drm/i915/display/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -7793,7 +7793,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv) 
	struct intel_encoder *encoder;

	bool dpd_is_edp = false;



	intel_pps_unlock_regs_wa(dev_priv);

	intel_pps_unlock_regs_wa(display);



	if (!HAS_DISPLAY(dev_priv))

		return;