Commit eb9d6256 authored by Bokun Zhang's avatar Bokun Zhang Committed by Alex Deucher
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drm/amd/amdgpu/vcn: Add RB decouple feature under SRIOV - P3 



- Update VCN header for RB decouple feature
- Add metadata struct, metadata will be placed after each RB

Signed-off-by: default avatarBokun Zhang <bokun.zhang@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fc313673

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+41 −7
Original line number Diff line number Diff line
@@ -169,6 +169,9 @@ 
#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)

#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)

#define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14)

#define AMDGPU_VCN_VF_RB_DECOUPLE_FLAG (1 << 15)



#define MAX_NUM_VCN_RB_SETUP 4



#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER	0x00000001

#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER		0x00000001
@@ -335,8 +338,17 @@ struct amdgpu_fw_shared { 
	struct amdgpu_fw_shared_smu_interface_info smu_interface_info;

};



struct amdgpu_vcn_rb_setup_info {

	uint32_t  rb_addr_lo;

	uint32_t  rb_addr_hi;

	uint32_t  rb_size;

};



struct amdgpu_fw_shared_rb_setup {

	uint32_t is_rb_enabled_flags;



	union {

		struct {

			uint32_t rb_addr_lo;

			uint32_t rb_addr_hi;

			uint32_t  rb_size;
@@ -346,11 +358,22 @@ struct amdgpu_fw_shared_rb_setup { 
			uint32_t  reserved[6];

		};



		struct {

			struct amdgpu_vcn_rb_setup_info rb_info[MAX_NUM_VCN_RB_SETUP];

		};

	};

};



struct amdgpu_fw_shared_drm_key_wa {

	uint8_t  method;

	uint8_t  reserved[3];

};



struct amdgpu_fw_shared_queue_decouple {

	uint8_t  is_enabled;

	uint8_t  reserved[7];

};



struct amdgpu_vcn4_fw_shared {

	uint32_t present_flag_0;

	uint8_t pad[12];
@@ -361,6 +384,8 @@ struct amdgpu_vcn4_fw_shared { 
	struct amdgpu_fw_shared_rb_setup rb_setup;

	struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;

	struct amdgpu_fw_shared_drm_key_wa drm_key_wa;

	uint8_t pad3[9];

	struct amdgpu_fw_shared_queue_decouple decouple;

};



struct amdgpu_vcn_fwlog {
@@ -378,6 +403,15 @@ struct amdgpu_vcn_decode_buffer { 
	uint32_t pad[30];

};



struct amdgpu_vcn_rb_metadata {

	uint32_t size;

	uint32_t present_flag_0;



	uint8_t version;

	uint8_t ring_id;

	uint8_t pad[26];

};



#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80

#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40

#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0