Loading drivers/gpu/drm/amd/display/dmub/src/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,7 @@ DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o DMUB += dmub_dcn31.o dmub_dcn314.o dmub_dcn315.o dmub_dcn316.o DMUB += dmub_dcn32.o DMUB += dmub_dcn35.o DMUB += dmub_dcn351.o AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB)) Loading drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c 0 → 100644 +34 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: MIT */ /* Copyright 2024 Advanced Micro Devices, Inc. */ #include "../dmub_srv.h" #include "dmub_reg.h" #include "dmub_dcn351.h" #include "dcn/dcn_3_5_1_offset.h" #include "dcn/dcn_3_5_1_sh_mask.h" #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] #define CTX dmub #define REGS dmub->regs_dcn35 #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) { struct dmub_srv_dcn35_regs *regs = dmub->regs_dcn35; #define REG_STRUCT regs #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); DMUB_DCN35_REGS() DMCUB_INTERNAL_REGS() #undef DMUB_SR #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); DMUB_DCN35_FIELDS() #undef DMUB_SF #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); DMUB_DCN35_FIELDS() #undef DMUB_SF #undef REG_STRUCT } drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.h 0 → 100644 +13 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: MIT */ /* Copyright 2024 Advanced Micro Devices, Inc. */ #ifndef _DMUB_DCN351_H_ #define _DMUB_DCN351_H_ #include "dmub_dcn35.h" struct dmub_srv; void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx); #endif /* _DMUB_DCN351_H_ */ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +4 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,7 @@ #include "dmub_dcn316.h" #include "dmub_dcn32.h" #include "dmub_dcn35.h" #include "dmub_dcn351.h" #include "os_types.h" /* * Note: the DMUB service is standalone. No additional headers should be Loading Loading @@ -315,6 +316,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) break; case DMUB_ASIC_DCN35: case DMUB_ASIC_DCN351: dmub->regs_dcn35 = &dmub_srv_dcn35_regs; funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory; funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd; Loading Loading @@ -351,6 +353,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; if (asic == DMUB_ASIC_DCN351) funcs->init_reg_offsets = dmub_srv_dcn351_regs_init; funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; funcs->should_detect = dmub_dcn35_should_detect; Loading Loading
drivers/gpu/drm/amd/display/dmub/src/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,7 @@ DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o DMUB += dmub_dcn31.o dmub_dcn314.o dmub_dcn315.o dmub_dcn316.o DMUB += dmub_dcn32.o DMUB += dmub_dcn35.o DMUB += dmub_dcn351.o AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB)) Loading
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c 0 → 100644 +34 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: MIT */ /* Copyright 2024 Advanced Micro Devices, Inc. */ #include "../dmub_srv.h" #include "dmub_reg.h" #include "dmub_dcn351.h" #include "dcn/dcn_3_5_1_offset.h" #include "dcn/dcn_3_5_1_sh_mask.h" #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] #define CTX dmub #define REGS dmub->regs_dcn35 #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) { struct dmub_srv_dcn35_regs *regs = dmub->regs_dcn35; #define REG_STRUCT regs #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); DMUB_DCN35_REGS() DMCUB_INTERNAL_REGS() #undef DMUB_SR #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); DMUB_DCN35_FIELDS() #undef DMUB_SF #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); DMUB_DCN35_FIELDS() #undef DMUB_SF #undef REG_STRUCT }
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.h 0 → 100644 +13 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: MIT */ /* Copyright 2024 Advanced Micro Devices, Inc. */ #ifndef _DMUB_DCN351_H_ #define _DMUB_DCN351_H_ #include "dmub_dcn35.h" struct dmub_srv; void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx); #endif /* _DMUB_DCN351_H_ */
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +4 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,7 @@ #include "dmub_dcn316.h" #include "dmub_dcn32.h" #include "dmub_dcn35.h" #include "dmub_dcn351.h" #include "os_types.h" /* * Note: the DMUB service is standalone. No additional headers should be Loading Loading @@ -315,6 +316,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) break; case DMUB_ASIC_DCN35: case DMUB_ASIC_DCN351: dmub->regs_dcn35 = &dmub_srv_dcn35_regs; funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory; funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd; Loading Loading @@ -351,6 +353,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; if (asic == DMUB_ASIC_DCN351) funcs->init_reg_offsets = dmub_srv_dcn351_regs_init; funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; funcs->should_detect = dmub_dcn35_should_detect; Loading