Commit ebb3acf4 authored by Ovidiu Panait's avatar Ovidiu Panait Committed by Geert Uytterhoeven
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clk: renesas: r9a09g056: Add clock and reset entries for TSU 



Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2N (R9A09G056) SoC.

Signed-off-by: default avatarOvidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251209091115.8541-3-ovidiu.panait.rb@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 2efea3b3

drivers/clk/renesas/r9a09g056-cpg.c

+6 −0
Original line number Diff line number Diff line
@@ -537,6 +537,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("gpu_0_ace_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,

						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("tsu_0_pclk",			CLK_QEXTAL, 16, 9, 8, 9,

						BUS_MSTOP(5, BIT(2))),

	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,

						BUS_MSTOP(2, BIT(15))),

};



static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
@@ -626,6 +630,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 
	DEF_RST(13, 13, 6, 14),		/* GPU_0_RESETN */

	DEF_RST(13, 14, 6, 15),		/* GPU_0_AXI_RESETN */

	DEF_RST(13, 15, 6, 16),		/* GPU_0_ACE_RESETN */

	DEF_RST(15, 7, 7, 8),		/* TSU_0_PRESETN */

	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */

};



const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {