Commit ebca3970 authored by Dario Binacchi's avatar Dario Binacchi Committed by Stephen Boyd
Browse files

dt-bindings: clock: convert stm32 rcc bindings to json-schema 



The patch converts st,stm32-rcc.txt to the JSON schema, but it does more
than that. The old bindings, in fact, only covered the stm32f{4,7}
platforms and not the stm32h7. Therefore, to avoid patch submission tests
failing, it was necessary to add the corresponding compatible (i. e.
st,stm32h743-rcc) and specify that, in this case, 3 are the clocks instead
of the 2 required for the stm32f{4,7} platforms.
Additionally, the old bindings made no mention of the st,syscfg property,
which is used by both the stm32f{4,7} and the stm32h7 platforms.

The patch also fixes the files referencing to the old st,stm32-rcc.txt.

Signed-off-by: default avatarDario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Link: https://lore.kernel.org/r/20250114182021.670435-2-dario.binacchi@amarulasolutions.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 40384c84

Documentation/devicetree/bindings/clock/st,stm32-rcc.txt

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STMicroelectronics STM32 Reset and Clock Controller

===================================================



The RCC IP is both a reset and a clock controller.



Please refer to clock-bindings.txt for common clock controller binding usage.

Please also refer to reset.txt for common reset controller binding usage.



Required properties:

- compatible: Should be:

  "st,stm32f42xx-rcc"

  "st,stm32f469-rcc"

  "st,stm32f746-rcc"

  "st,stm32f769-rcc"



- reg: should be register base and length as documented in the

  datasheet

- #reset-cells: 1, see below

- #clock-cells: 2, device nodes should specify the clock in their "clocks"

  property, containing a phandle to the clock device node, an index selecting

  between gated clocks and other clocks and an index specifying the clock to

  use.

- clocks: External oscillator clock phandle

  - high speed external clock signal (HSE)

  - external I2S clock (I2S_CKIN)



Example:



	rcc: rcc@40023800 {

		#reset-cells = <1>;

		#clock-cells = <2>

		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";

		reg = <0x40023800 0x400>;

		clocks = <&clk_hse>, <&clk_i2s_ckin>;

	};



Specifying gated clocks

=======================



The primary index must be set to 0.



The secondary index is the bit number within the RCC register bank, starting

from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).



It is calculated as: index = register_offset / 4 * 32 + bit_offset.

Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).



To simplify the usage and to share bit definition with the reset and clock

drivers of the RCC IP, macros are available to generate the index in

human-readble format.



For STM32F4 series, the macro are available here:

 - include/dt-bindings/mfd/stm32f4-rcc.h



Example:



	/* Gated clock, AHB1 bit 0 (GPIOA) */

	... {

		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>

	};



	/* Gated clock, AHB2 bit 4 (CRYP) */

	... {

		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>

	};



Specifying other clocks

=======================



The primary index must be set to 1.



The secondary index is bound with the following magic numbers:



	0	SYSTICK

	1	FCLK

	2	CLK_LSI		(low-power clock source)

	3	CLK_LSE		(generated from a 32.768 kHz low-speed external

				 crystal or ceramic resonator)

	4	CLK_HSE_RTC	(HSE division factor for RTC clock)

	5	CLK_RTC		(real-time clock)

	6	PLL_VCO_I2S	(vco frequency of I2S pll)

	7	PLL_VCO_SAI	(vco frequency of SAI pll)

	8	CLK_LCD		(LCD-TFT)

	9	CLK_I2S		(I2S clocks)

	10	CLK_SAI1	(audio clocks)

	11	CLK_SAI2

	12	CLK_I2SQ_PDIV	(post divisor of pll i2s q divisor)

	13	CLK_SAIQ_PDIV	(post divisor of pll sai q divisor)



	14	CLK_HSI		(Internal ocscillator clock)

	15	CLK_SYSCLK	(System Clock)

	16	CLK_HDMI_CEC	(HDMI-CEC clock)

	17	CLK_SPDIF	(SPDIF-Rx clock)

	18	CLK_USART1	(U(s)arts clocks)

	19	CLK_USART2

	20	CLK_USART3

	21	CLK_UART4

	22	CLK_UART5

	23	CLK_USART6

	24	CLK_UART7

	25	CLK_UART8

	26	CLK_I2C1	(I2S clocks)

	27	CLK_I2C2

	28	CLK_I2C3

	29	CLK_I2C4

	30	CLK_LPTIMER	(LPTimer1 clock)

	31	CLK_PLL_SRC

	32	CLK_DFSDM1

	33	CLK_ADFSDM1

	34	CLK_F769_DSI

)



Example:



	/* Misc clock, FCLK */

	... {

		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>

	};





Specifying softreset control of devices

=======================================



Device nodes should specify the reset channel required in their "resets"

property, containing a phandle to the reset device node and an index specifying

which channel to use.

The index is the bit number within the RCC registers bank, starting from RCC

base address.

It is calculated as: index = register_offset / 4 * 32 + bit_offset.

Where bit_offset is the bit offset within the register.

For example, for CRC reset:

  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140



example:



	timer2 {

		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;

	};

Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: STMicroelectronics STM32 Reset Clock Controller



maintainers:

  - Dario Binacchi <dario.binacchi@amarulasolutions.com>



description: |

  The RCC IP is both a reset and a clock controller.

  The reset phandle argument is the bit number within the RCC registers bank,

  starting from RCC base address.



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - st,stm32f42xx-rcc

              - st,stm32f746-rcc

              - st,stm32h743-rcc

          - const: st,stm32-rcc

      - items:

          - enum:

              - st,stm32f469-rcc

          - const: st,stm32f42xx-rcc

          - const: st,stm32-rcc

      - items:

          - enum:

              - st,stm32f769-rcc

          - const: st,stm32f746-rcc

          - const: st,stm32-rcc



  reg:

    maxItems: 1



  '#reset-cells':

    const: 1



  '#clock-cells':

    enum: [1, 2]



  clocks:

    minItems: 2

    maxItems: 3



  st,syscfg:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to system configuration controller. It can be used to control the

      power domain circuitry.



required:

  - compatible

  - reg

  - '#reset-cells'

  - '#clock-cells'

  - clocks

  - st,syscfg



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: st,stm32h743-rcc

    then:

      properties:

        '#clock-cells':

          const: 1

          description: |

            The clock index for the specified type.

        clocks:

          items:

            - description: high speed external (HSE) clock input

            - description: low speed external (LSE) clock input

            - description: Inter-IC sound (I2S) clock input

    else:

      properties:

        '#clock-cells':

          const: 2

          description: |

            - The first cell is the clock type, possible values are 0 for

              gated clocks and 1 otherwise.

            - The second cell is the clock index for the specified type.

        clocks:

          items:

            - description: high speed external (HSE) clock input

            - description: Inter-IC sound (I2S) clock input



additionalProperties: false



examples:

  # Reset and Clock Control Module node:

  - |

    clock-controller@58024400 {

        compatible = "st,stm32h743-rcc", "st,stm32-rcc";

        reg = <0x58024400 0x400>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;

        st,syscfg = <&pwrcfg>;

    };



...

Documentation/devicetree/bindings/reset/st,stm32-rcc.txt

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@@ -3,4 +3,4 @@ STMicroelectronics STM32 Peripheral Reset Controller 


The RCC IP is both a reset and a clock controller.



Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
 
Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml

include/dt-bindings/clock/stm32fx-clock.h

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@@ -10,7 +10,7 @@ 
 * List of clocks which are not derived from system clock (SYSCLOCK)

 *

 * The index of these clocks is the secondary index of DT bindings

 * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)

 * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml)

 *

 * e.g:

	<assigned-clocks = <&rcc 1 CLK_LSE>;