Commit ebcfbf02 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-updates-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux 

Pull iommu updates from Will Deacon:
 "Core:

   - Support for the "ats-supported" device-tree property

   - Removal of the 'ops' field from 'struct iommu_fwspec'

   - Introduction of iommu_paging_domain_alloc() and partial conversion
     of existing users

   - Introduce 'struct iommu_attach_handle' and provide corresponding
     IOMMU interfaces which will be used by the IOMMUFD subsystem

   - Remove stale documentation

   - Add missing MODULE_DESCRIPTION() macro

   - Misc cleanups

  Allwinner Sun50i:

   - Ensure bypass mode is disabled on H616 SoCs

   - Ensure page-tables are allocated below 4GiB for the 32-bit
     page-table walker

   - Add new device-tree compatible strings

  AMD Vi:

   - Use try_cmpxchg64() instead of cmpxchg64() when updating pte

  Arm SMMUv2:

   - Print much more useful information on context faults

   - Fix Qualcomm TBU probing when CONFIG_ARM_SMMU_QCOM_DEBUG=n

   - Add new Qualcomm device-tree bindings

  Arm SMMUv3:

   - Support for hardware update of access/dirty bits and reporting via
     IOMMUFD

   - More driver rework from Jason, this time updating the PASID/SVA
     support to prepare for full IOMMUFD support

   - Add missing MODULE_DESCRIPTION() macro

   - Minor fixes and cleanups

  NVIDIA Tegra:

   - Fix for benign fwspec initialisation issue exposed by rework on the
     core branch

  Intel VT-d:

   - Use try_cmpxchg64() instead of cmpxchg64() when updating pte

   - Use READ_ONCE() to read volatile descriptor status

   - Remove support for handling Execute-Requested requests

   - Avoid calling iommu_domain_alloc()

   - Minor fixes and refactoring

  Qualcomm MSM:

   - Updates to the device-tree bindings"

* tag 'iommu-updates-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (72 commits)
  iommu/tegra-smmu: Pass correct fwnode to iommu_fwspec_init()
  iommu/vt-d: Fix identity map bounds in si_domain_init()
  iommu: Move IOMMU_DIRTY_NO_CLEAR define
  dt-bindings: iommu: Convert msm,iommu-v0 to yaml
  iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()
  iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH
  docs: iommu: Remove outdated Documentation/userspace-api/iommu.rst
  arm64: dts: fvp: Enable PCIe ATS for Base RevC FVP
  iommu/of: Support ats-supported device-tree property
  dt-bindings: PCI: generic: Add ats-supported property
  iommu: Remove iommu_fwspec ops
  OF: Simplify of_iommu_configure()
  ACPI: Retire acpi_iommu_fwspec_ops()
  iommu: Resolve fwspec ops automatically
  iommu/mediatek-v1: Clean up redundant fwspec checks
  RDMA/usnic: Use iommu_paging_domain_alloc()
  wifi: ath11k: Use iommu_paging_domain_alloc()
  wifi: ath10k: Use iommu_paging_domain_alloc()
  drm/msm: Use iommu_paging_domain_alloc()
  vhost-vdpa: Use iommu_paging_domain_alloc()
  ...
parents 3d515209 8b6c32e8

Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml

+6 −1
Original line number Diff line number Diff line
@@ -17,7 +17,12 @@ properties: 
      The content of the cell is the master ID.



  compatible:

    const: allwinner,sun50i-h6-iommu

    oneOf:

      - const: allwinner,sun50i-h6-iommu

      - const: allwinner,sun50i-h616-iommu

      - items:

          - const: allwinner,sun55i-a523-iommu

          - const: allwinner,sun50i-h616-iommu



  reg:

    maxItems: 1

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

+4 −2
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ properties: 
              - qcom,qcm2290-smmu-500

              - qcom,sa8775p-smmu-500

              - qcom,sc7280-smmu-500

              - qcom,sc8180x-smmu-500

              - qcom,sc8280xp-smmu-500

              - qcom,sm6115-smmu-500

              - qcom,sm6125-smmu-500
@@ -95,6 +96,7 @@ properties: 
              - qcom,sm8450-smmu-500

              - qcom,sm8550-smmu-500

              - qcom,sm8650-smmu-500

              - qcom,x1e80100-smmu-500

          - const: qcom,adreno-smmu

          - const: qcom,smmu-500

          - const: arm,mmu-500
@@ -415,6 +417,7 @@ allOf: 
        compatible:

          contains:

            enum:

              - qcom,sc8180x-smmu-500

              - qcom,sm6350-smmu-v2

              - qcom,sm7150-smmu-v2

              - qcom,sm8150-smmu-500
@@ -520,6 +523,7 @@ allOf: 
            - enum:

                - qcom,sm8550-smmu-500

                - qcom,sm8650-smmu-500

                - qcom,x1e80100-smmu-500

            - const: qcom,adreno-smmu

            - const: qcom,smmu-500

            - const: arm,mmu-500
@@ -550,14 +554,12 @@ allOf: 
              - nvidia,smmu-500

              - qcom,qdu1000-smmu-500

              - qcom,sc7180-smmu-500

              - qcom,sc8180x-smmu-500

              - qcom,sdm670-smmu-500

              - qcom,sdm845-smmu-500

              - qcom,sdx55-smmu-500

              - qcom,sdx65-smmu-500

              - qcom,sm6350-smmu-500

              - qcom,sm6375-smmu-500

              - qcom,x1e80100-smmu-500

    then:

      properties:

        clock-names: false

Documentation/devicetree/bindings/iommu/msm,iommu-v0.txt

deleted100644 → 0
+0 −64
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* QCOM IOMMU



The MSM IOMMU is an implementation compatible with the ARM VMSA short

descriptor page tables. It provides address translation for bus masters outside

of the CPU, each connected to the IOMMU through a port called micro-TLB.



Required Properties:



  - compatible: Must contain "qcom,apq8064-iommu".

  - reg: Base address and size of the IOMMU registers.

  - interrupts: Specifiers for the MMU fault interrupts. For instances that

    support secure mode two interrupts must be specified, for non-secure and

    secure mode, in that order. For instances that don't support secure mode a

    single interrupt must be specified.

  - #iommu-cells: The number of cells needed to specify the stream id. This

		  is always 1.

  - qcom,ncb:	  The total number of context banks in the IOMMU.

  - clocks	: List of clocks to be used during SMMU register access. See

		  Documentation/devicetree/bindings/clock/clock-bindings.txt

		  for information about the format. For each clock specified

		  here, there must be a corresponding entry in clock-names

		  (see below).



  - clock-names	: List of clock names corresponding to the clocks specified in

		  the "clocks" property (above).

		  Should be "smmu_pclk" for specifying the interface clock

		  required for iommu's register accesses.

		  Should be "smmu_clk" for specifying the functional clock

		  required by iommu for bus accesses.



Each bus master connected to an IOMMU must reference the IOMMU in its device

node with the following property:



  - iommus: A reference to the IOMMU in multiple cells. The first cell is a

	    phandle to the IOMMU and the second cell is the stream id.

	    A single master device can be connected to more than one iommu

	    and multiple contexts in each of the iommu. So multiple entries

	    are required to list all the iommus and the stream ids that the

	    master is connected to.



Example: mdp iommu and its bus master



                mdp_port0: iommu@7500000 {

			compatible = "qcom,apq8064-iommu";

			#iommu-cells = <1>;

			clock-names =

			    "smmu_pclk",

			    "smmu_clk";

			clocks =

			    <&mmcc SMMU_AHB_CLK>,

			    <&mmcc MDP_AXI_CLK>;

			reg = <0x07500000 0x100000>;

			interrupts =

			    <GIC_SPI 63 0>,

			    <GIC_SPI 64 0>;

			qcom,ncb = <2>;

		};



		mdp: qcom,mdp@5100000 {

			compatible = "qcom,mdp";

			...

			iommus = <&mdp_port0 0

				  &mdp_port0 2>;

		};

Documentation/devicetree/bindings/iommu/qcom,apq8064-iommu.yaml

0 → 100644
+78 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---



$id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm APQ8064 IOMMU



maintainers:

  - David Heidelberg <david@ixit.cz>



description:

  The MSM IOMMU is an implementation compatible with the ARM VMSA short

  descriptor page tables. It provides address translation for bus masters

  outside of the CPU, each connected to the IOMMU through a port called micro-TLB.



properties:

  compatible:

    const: qcom,apq8064-iommu



  clocks:

    items:

      - description: interface clock for register accesses

      - description: functional clock for bus accesses



  clock-names:

    items:

      - const: smmu_pclk

      - const: iommu_clk



  reg:

    maxItems: 1



  interrupts:

    description: Specifiers for the MMU fault interrupts.

    minItems: 1

    items:

      - description: non-secure mode interrupt

      - description: secure mode interrupt (for instances which supports it)



  "#iommu-cells":

    const: 1

    description: Each IOMMU specifier describes a single Stream ID.



  qcom,ncb:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: The total number of context banks in the IOMMU.

    minimum: 1

    maximum: 4



required:

  - reg

  - interrupts

  - clocks

  - clock-names

  - qcom,ncb



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,mmcc-msm8960.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    iommu@7500000 {

            compatible = "qcom,apq8064-iommu";

            reg = <0x07500000 0x100000>;

            interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

            clocks = <&clk SMMU_AHB_CLK>,

                     <&clk MDP_AXI_CLK>;

            clock-names = "smmu_pclk",

                          "iommu_clk";

            #iommu-cells = <1>;

            qcom,ncb = <2>;

    };

Documentation/devicetree/bindings/iommu/qcom,iommu.yaml

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ properties: 
          - const: qcom,msm-iommu-v1

      - items:

          - enum:

              - qcom,msm8953-iommu

              - qcom,msm8976-iommu

          - const: qcom,msm-iommu-v2