dt-bindings: pinctrl: qcom: Add Glymur pinctrl

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/qcom,glymur-tlmm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. Glymur TLMM block

maintainers:

  - Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>

description:

  Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC.

allOf:

  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:

  compatible:

    const: qcom,glymur-tlmm

  reg:

    maxItems: 1

  interrupts:

    maxItems: 1

  gpio-reserved-ranges:

    minItems: 1

    maxItems: 125

  gpio-line-names:

    maxItems: 250

patternProperties:

  "-state$":

    oneOf:

      - $ref: "#/$defs/qcom-glymur-tlmm-state"

      - patternProperties:

          "-pins$":

            $ref: "#/$defs/qcom-glymur-tlmm-state"

        additionalProperties: false

$defs:

  qcom-glymur-tlmm-state:

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.

    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    unevaluatedProperties: false

    properties:

      pins:

        description:

          List of gpio pins affected by the properties specified in this

          subnode.

        items:

          oneOf:

            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-4][0-9])$"

            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]

        minItems: 1

        maxItems: 36

      function:

        description:

          Specify the alternative function to be configured for the specified

          pins.

        enum: [ gpio, resout_gpio_n, aoss_cti, asc_cci, atest_char, atest_usb,

                audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, cam_asc_mclk4,

                cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer,

                cmu_rng, cri_trng, dbg_out_clk, ddr_bist_complete,

                ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi,

                edp0_hot, edp0_lcd, edp1_lcd, egpio, eusb0_ac_en, eusb1_ac_en,

                eusb2_ac_en, eusb3_ac_en, eusb5_ac_en, eusb6_ac_en, gcc_gp1,

                gcc_gp2, gcc_gp3, host2wlan_sol, i2c0_s_scl, i2c0_s_sda,

                i2s0_data, i2s0_sck, i2s0_ws, i2s1_data, i2s1_sck, i2s1_ws,

                ibi_i3c, jitter_bist, mdp_vsync_out, mdp_vsync_e, mdp_vsync_p,

                mdp_vsync_s, pcie3a_clk, pcie3a_rst_n, pcie3b_clk,

                pcie4_clk_req_n, pcie5_clk_req_n, pcie6_clk_req_n, phase_flag,

                pll_bist_sync, pll_clk_aux, pmc_oca_n, pmc_uva_n, prng_rosc,

                qdss_cti, qdss_gpio, qspi, qup0_se0, qup0_se1, qup0_se2,

                qup0_se3_l0, qup0_se3, qup0_se4, qup0_se5, qup0_se6, qup0_se7,

                qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5,

                qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3,

                qup2_se4, qup2_se5, qup2_se6, qup2_se7, qup3_se0, qup3_se1,

                sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data, smb_acok_n,

                sys_throttle, tb_trig_sdc2, tb_trig_sdc4, tmess_prng,

                tsense_pwm, tsense_therm, usb0_dp, usb0_phy_ps, usb0_sbrx,

                usb0_sbtx, usb0_tmu, usb1_dbg, usb1_dp, usb1_phy_ps, usb1_sbrx,

                usb1_sbtx, usb1_tmu, usb2_dp, usb2_phy_ps, usb2_sbrx, usb2_sbtx,

                usb2_tmu, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]

    required:

      - pins

required:

  - compatible

  - reg

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@f100000 {

        compatible = "qcom,glymur-tlmm";

        reg = <0x0f100000 0xf00000>;

        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        gpio-controller;

        #gpio-cells = <2>;

        interrupt-controller;

        #interrupt-cells = <2>;

        gpio-ranges = <&tlmm 0 0 249>;

        wakeup-parent = <&pdc>;

        gpio-reserved-ranges = <4 4>, <10 2>, <33 3>, <44 4>;

        qup_uart21_default: qup-uart21-default-state {

            tx-pins {

                pins = "gpio86";

                function = "qup2_se5";

                drive-strength = <2>;

                bias-disable;

            };

            rx-pins {

                pins = "gpio87";

                function = "qup2_se5";

                drive-strength = <2>;

                bias-disable;

            };

        };

    };

...