Commit ec0b62cc authored Oct 31, 2025 by Linus Torvalds

kernel

Pull drm fixes from Simona Vetter:
 "Looks like stochastics conspired to make this one a bit bigger, but
  nothing scary at all. Also first examples of the new Link: tags, yay!

  Next week Dave should be back.

  Drivers:
   - mediatek: uaf in unbind, fixes -rc2 boot regression
   - radeon: devm conversion fixes
   - amdgpu: VPE idle handler, re-enable DM idle optimization, DCN3,
     SMU, vblank, HDP eDP, powerplay fixes for fiji/iceland
   - msm: bunch of gem error path fixes, gmu fw parsing fix, dpu fixes
   - intel: fix dmc/dc6 asserts on ADL-S
   - xe: fix xe_validation_guard(), wake device handling around gt reset
   - ast: fix display output on AST2300
   - etnaviv: fix gpu flush
   - imx: fix parallel bridge handling
   - nouveau: scheduler locking fix
   - panel: fixes for kingdisplay-kd097d04 and sitronix-st7789v

  Core Changes:
   - CI: disable broken sanity job
   - sysfb: fix NULL pointer access
   - sched: fix SIGKILL handling, locking for race condition
   - dma_fence: better timeline name for signalled fences"

* tag 'drm-fixes-2025-10-31' of https://gitlab.freedesktop.org/drm/kernel: (44 commits)
  drm/ast: Clear preserved bits from register output value
  drm/imx: parallel-display: add the bridge before attaching it
  drm/imx: parallel-display: convert to devm_drm_bridge_alloc() API
  drm/panel: kingdisplay-kd097d04: Disable EoTp
  drm/panel: sitronix-st7789v: fix sync flags for t28cp45tn89
  drm/xe: Do not wake device during a GT reset
  drm/xe: Fix uninitialized return value from xe_validation_guard()
  drm/msm/dpu: Fix adjusted mode clock check for 3d merge
  drm/msm/dpu: Disable broken YUV on QSEED2 hardware
  drm/msm/dpu: Require linear modifier for writeback framebuffers
  drm/msm/dpu: Fix pixel extension sub-sampling
  drm/msm/dpu: Disable scaling for unsupported scaler types
  drm/msm/dpu: Propagate error from dpu_assign_plane_resources
  drm/msm/dpu: Fix allocation of RGB SSPPs without scaling
  drm/msm: dsi: fix PLL init in bonded mode
  drm/i915/dmc: Clear HRR EVT_CTL/HTP to zero on ADL-S
  drm/amd/display: Fix incorrect return of vblank enable on unconfigured crtc
  drm/amd/display: Add HDR workaround for a specific eDP
  drm/amdgpu: fix SPDX header on cyan_skillfish_reg_init.c
  drm/amdgpu: fix SPDX header on irqsrcs_vcn_5_0.h
  ...

parents f414f9fd 41dacb39

drivers/dma-buf/dma-fence.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1141,7 +1141,7 @@ const char __rcu dma_fence_timeline_name(struct dma_fence fence)
		"RCU protection is required for safe access to returned string");

		if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
		return fence->ops->get_driver_name(fence);
		return fence->ops->get_timeline_name(fence);
		else
		return "signaled-timeline";
		}

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c

+1 −1

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0
		// SPDX-License-Identifier: MIT
		/*
		* Copyright 2025 Advanced Micro Devices, Inc.
		*

drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h

+1 −1

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		/* SPDX-License-Identifier: MIT */
		/*
		* Copyright 2025 Advanced Micro Devices, Inc.
		*

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

+30 −4

Original line number	Diff line number	Diff line
		@@ -322,6 +322,26 @@ static int vpe_early_init(struct amdgpu_ip_block *ip_block)
		return 0;
		}

		static bool vpe_need_dpm0_at_power_down(struct amdgpu_device *adev)
		{
		switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
		case IP_VERSION(6, 1, 1):
		return adev->pm.fw_version < 0x0a640500;
		default:
		return false;
		}
		}

		static int vpe_get_dpm_level(struct amdgpu_device *adev)
		{
		struct amdgpu_vpe *vpe = &adev->vpe;

		if (!adev->pm.dpm_enabled)
		return 0;

		return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv));
		}

		static void vpe_idle_work_handler(struct work_struct *work)
		{
		struct amdgpu_device *adev =
		@@ -329,10 +349,16 @@ static void vpe_idle_work_handler(struct work_struct *work)
		unsigned int fences = 0;

		fences += amdgpu_fence_count_emitted(&adev->vpe.ring);
		if (fences)
		goto reschedule;

		if (vpe_need_dpm0_at_power_down(adev) && vpe_get_dpm_level(adev) != 0)
		goto reschedule;

		if (fences == 0)
		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
		else
		return;

		reschedule:
		schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
		}

drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c

+1 −1

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0
		// SPDX-License-Identifier: MIT
		/*
		* Copyright 2018 Advanced Micro Devices, Inc.
		*