Commit ec0c2d53 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of https://github.com/openrisc/linux 

Pull OpenRISC updates from Stafford Horne:

 - Support for cacheinfo API to expose OpenRISC cache info via sysfs,
   this also translated to some cleanups to OpenRISC cache flush and
   invalidate API's

 - Documentation updates for new mailing list and toolchain binaries

* tag 'for-linus' of https://github.com/openrisc/linux:
  Documentation: openrisc: Update toolchain binaries URL
  Documentation: openrisc: Update mailing list
  openrisc: Add cacheinfo support
  openrisc: Introduce new utility functions to flush and invalidate caches
  openrisc: Refactor struct cpuinfo_or1k to reduce duplication
parents a16ebe51 66ffd2f3

Documentation/arch/openrisc/openrisc_port.rst

+6 −6
Original line number Diff line number Diff line
@@ -7,10 +7,10 @@ target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k). 


For information about OpenRISC processors and ongoing development:



	=======		=============================

	=======		==============================

	website		https://openrisc.io

	email		openrisc@lists.librecores.org

	=======		=============================

	email		linux-openrisc@vger.kernel.org

	=======		==============================



---------------------------------------------------------------------
@@ -27,11 +27,11 @@ Toolchain binaries can be obtained from openrisc.io or our github releases page. 
Instructions for building the different toolchains can be found on openrisc.io

or Stafford's toolchain build and release scripts.



	==========	=================================================

	binaries	https://github.com/openrisc/or1k-gcc/releases

	==========	==========================================================

	binaries	https://github.com/stffrdhrn/or1k-toolchain-build/releases

	toolchains	https://openrisc.io/software

	building	https://github.com/stffrdhrn/or1k-toolchain-build

	==========	=================================================

	==========	==========================================================



2) Building

Documentation/translations/zh_CN/arch/openrisc/openrisc_port.rst

+6 −6
Original line number Diff line number Diff line
@@ -17,10 +17,10 @@ OpenRISC 1000系列（或1k）。 


关于OpenRISC处理器和正在进行中的开发的信息:



	=======		=============================

	=======		==============================

	网站		https://openrisc.io

	邮箱		openrisc@lists.librecores.org

	=======		=============================

	邮箱		linux-openrisc@vger.kernel.org

	=======		==============================



---------------------------------------------------------------------
@@ -36,11 +36,11 @@ OpenRISC工具链和Linux的构建指南 
工具链的构建指南可以在openrisc.io或Stafford的工具链构建和发布脚本

中找到。



	======      =================================================

	二进制      https://github.com/openrisc/or1k-gcc/releases

	======      ==========================================================

	二进制      https://github.com/stffrdhrn/or1k-toolchain-build/releases

	工具链      https://openrisc.io/software

	构建        https://github.com/stffrdhrn/or1k-toolchain-build

	======      =================================================

	======      ==========================================================



2) 构建

Documentation/translations/zh_TW/arch/openrisc/openrisc_port.rst

+6 −6
Original line number Diff line number Diff line
@@ -17,10 +17,10 @@ OpenRISC 1000系列（或1k）。 


關於OpenRISC處理器和正在進行中的開發的信息:



	=======		=============================

	=======		==============================

	網站		https://openrisc.io

	郵箱		openrisc@lists.librecores.org

	=======		=============================

	郵箱		linux-openrisc@vger.kernel.org

	=======		==============================



---------------------------------------------------------------------
@@ -36,11 +36,11 @@ OpenRISC工具鏈和Linux的構建指南 
工具鏈的構建指南可以在openrisc.io或Stafford的工具鏈構建和發佈腳本

中找到。



	======      =================================================

	二進制      https://github.com/openrisc/or1k-gcc/releases

	======      ==========================================================

	二進制      https://github.com/stffrdhrn/or1k-toolchain-build/releases

	工具鏈      https://openrisc.io/software

	構建        https://github.com/stffrdhrn/or1k-toolchain-build

	======      =================================================

	======      ==========================================================



2) 構建

arch/openrisc/include/asm/cacheflush.h

+17 −0
Original line number Diff line number Diff line
@@ -23,6 +23,9 @@ 
 */

extern void local_dcache_page_flush(struct page *page);

extern void local_icache_page_inv(struct page *page);

extern void local_dcache_range_flush(unsigned long start, unsigned long end);

extern void local_dcache_range_inv(unsigned long start, unsigned long end);

extern void local_icache_range_inv(unsigned long start, unsigned long end);



/*

 * Data cache flushing always happen on the local cpu. Instruction cache
@@ -38,6 +41,20 @@ extern void local_icache_page_inv(struct page *page); 
extern void smp_icache_page_inv(struct page *page);

#endif /* CONFIG_SMP */



/*

 * Even if the actual block size is larger than L1_CACHE_BYTES, paddr

 * can be incremented by L1_CACHE_BYTES. When paddr is written to the

 * invalidate register, the entire cache line encompassing this address

 * is invalidated. Each subsequent reference to the same cache line will

 * not affect the invalidation process.

 */

#define local_dcache_block_flush(addr) \

	local_dcache_range_flush(addr, addr + L1_CACHE_BYTES)

#define local_dcache_block_inv(addr) \

	local_dcache_range_inv(addr, addr + L1_CACHE_BYTES)

#define local_icache_block_inv(addr) \

	local_icache_range_inv(addr, addr + L1_CACHE_BYTES)



/*

 * Synchronizes caches. Whenever a cpu writes executable code to memory, this

 * should be called to make sure the processor sees the newly written code.

arch/openrisc/include/asm/cpuinfo.h

+17 −7
Original line number Diff line number Diff line
@@ -15,16 +15,21 @@ 
#ifndef __ASM_OPENRISC_CPUINFO_H

#define __ASM_OPENRISC_CPUINFO_H



#include <asm/spr.h>

#include <asm/spr_defs.h>



struct cache_desc {

	u32 size;

	u32 sets;

	u32 block_size;

	u32 ways;

};



struct cpuinfo_or1k {

	u32 clock_frequency;



	u32 icache_size;

	u32 icache_block_size;

	u32 icache_ways;



	u32 dcache_size;

	u32 dcache_block_size;

	u32 dcache_ways;

	struct cache_desc icache;

	struct cache_desc dcache;



	u16 coreid;

};
@@ -32,4 +37,9 @@ struct cpuinfo_or1k { 
extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];

extern void setup_cpuinfo(void);



/*

 * Check if the cache component exists.

 */

extern bool cpu_cache_is_present(const unsigned int cache_type);



#endif /* __ASM_OPENRISC_CPUINFO_H */