Commit ec39a6d0 authored by Muhammad Ahmed's avatar Muhammad Ahmed Committed by Alex Deucher
Browse files

drm/amd/display: add debug option for ExtendedVBlank DLG adjust 



[why & how]
Add new option for debug usage

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarMuhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b5882675

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -979,6 +979,7 @@ struct dc_debug_options { 
	unsigned int ips2_eval_delay_us;

	unsigned int ips2_entry_delay_us;

	bool disable_timeout;

	bool disable_extblankadj;

};



struct gpu_info_soc_bounding_box_v1_0;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

+2 −1
Original line number Diff line number Diff line
@@ -2221,7 +2221,8 @@ void dcn20_optimize_bandwidth( 
			dc->clk_mgr,

			context,

			true);

	if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {

	if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &&

		!dc->debug.disable_extblankadj) {

		for (i = 0; i < dc->res_pool->pipe_count; ++i) {

			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];