Commit ec3e3976 authored Apr 13, 2026 by Gaghik Khachatrian Committed by Alex Deucher Apr 28, 2026

drm/amd/display: Update MCIF_ADDR macro to address IGT DWB regression



[Why]
A previous warning-fix commit updated type casts in the DCN3
mmhubbub code but missed updating the MCIF_ADDR macro to the
correct, fully parenthesized and casted version. This caused
a regression during DWB tests, where address values could be
misinterpreted, potentially leading to incorrect hardware
programming.

[How]
Updated the MCIF_ADDR macro in dcn30_mmhubbub.c to use the
proper parenthesization and type casting, ensuring correct
address handling. Removed redundant casts from REG_UPDATE
calls for improved clarity and consistency with current
coding standards.

Fixes: f4cdbb5d5405 ("drm/amd/display: Fix implicit narrowing conversion warnings")
Reviewed-by: Clayton King <clayton.king@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 4f251a5e9f2297023b00b7cab606de111931cfa3)

parent d2f272a3

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -40,8 +40,8 @@
		#define FN(reg_name, field_name) \
		mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name

		#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
		#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
		#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8))
		#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40))

		/* wbif programming guide:
		* 1. set up wbif parameter: