Commit ecd10702 authored Dec 01, 2023 by Nicholas Piggin Committed by Michael Ellerman Dec 07, 2023

KVM: PPC: Book3S HV: Handle pending exceptions on guest entry with MSR_EE



Commit 026728dc ("KVM: PPC: Book3S HV P9: Inject pending xive
interrupts at guest entry") changed guest entry so that if external
interrupts are enabled, BOOK3S_IRQPRIO_EXTERNAL is not tested for. Test
for this regardless of MSR_EE.

For an L1 host, do not inject an interrupt, but always
use LPCR_MER. If the L0 desires it can inject an interrupt.

Fixes: 026728dc ("KVM: PPC: Book3S HV P9: Inject pending xive interrupts at guest entry")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[jpn: use kvmpcc_get_msr(), write commit message]
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20231201132618.555031-7-vaibhav@linux.ibm.com

parent ec0f6639

arch/powerpc/kvm/book3s_hv.c

+12 −6

Original line number	Diff line number	Diff line
		@@ -4738,12 +4738,18 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,

		if (!nested) {
		kvmppc_core_prepare_to_enter(vcpu);
		if (__kvmppc_get_msr_hv(vcpu) & MSR_EE) {
		if (xive_interrupt_pending(vcpu))
		if (test_bit(BOOK3S_IRQPRIO_EXTERNAL,
		&vcpu->arch.pending_exceptions) \|\|
		xive_interrupt_pending(vcpu)) {
		/*
		* For nested HV, don't synthesize but always pass MER,
		* the L0 will be able to optimise that more
		* effectively than manipulating registers directly.
		*/
		if (!kvmhv_on_pseries() && (__kvmppc_get_msr_hv(vcpu) & MSR_EE))
		kvmppc_inject_interrupt_hv(vcpu,
		BOOK3S_INTERRUPT_EXTERNAL, 0);
		} else if (test_bit(BOOK3S_IRQPRIO_EXTERNAL,
		&vcpu->arch.pending_exceptions)) {
		else
		lpcr \|= LPCR_MER;
		}
		} else if (vcpu->arch.pending_exceptions \|\|