Commit ed651979 authored by Vladimir Kondratiev's avatar Vladimir Kondratiev Committed by Thomas Gleixner
Browse files

dt-bindings: interrupt-controller: Add MIPS P8700 aclint-sswi 



Add ACLINT-SSWI variant for the MIPS P8700 SoC. This CPU has a SSWI device
compliant with the RISC-V draft spec (see [1]).

CPU indexes on this platform are not continuous, instead it uses bit-fields
to encode hart,core,cluster numbers, thus the DT property
"riscv,hart-indexes" is mandatory for it.

Signed-off-by: default avatarVladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/all/20250612143911.3224046-4-vladimir.kondratiev@mobileye.com
Link: https://github.com/riscvarchive/riscv-aclint [1]
parent 81f335e1

Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml

+55 −9
Original line number Diff line number Diff line
@@ -4,23 +4,32 @@ 
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: T-HEAD C900 ACLINT Supervisor-level Software Interrupt Device

title: ACLINT Supervisor-level Software Interrupt Device



maintainers:

  - Inochi Amaoto <inochiama@outlook.com>



description:

  The SSWI device is a part of the THEAD ACLINT device. It provides

  supervisor-level IPI functionality for a set of HARTs on a THEAD

  platform. It provides a register to set an IPI (SETSSIP) for each

  HART connected to the SSWI device.

  The SSWI device is a part of the ACLINT device. It provides

  supervisor-level IPI functionality for a set of HARTs on a supported

  platforms. It provides a register to set an IPI (SETSSIP) for each

  HART connected to the SSWI device. See draft specification

  https://github.com/riscvarchive/riscv-aclint



  Following variants of the SSWI ACLINT supported, using dedicated

  compatible string

  - THEAD C900

  - MIPS P8700



properties:

  compatible:

    items:

    oneOf:

      - items:

          - enum:

              - sophgo,sg2044-aclint-sswi

          - const: thead,c900-aclint-sswi

      - items:

          - const: mips,p8700-aclint-sswi



  reg:

    maxItems: 1
@@ -34,6 +43,14 @@ properties: 
    minItems: 1

    maxItems: 4095



  riscv,hart-indexes:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    minItems: 1

    maxItems: 4095

    description:

      A list of hart indexes that APLIC should use to address each hart

      that is mentioned in the "interrupts-extended"



additionalProperties: false



required:
@@ -43,8 +60,22 @@ required: 
  - interrupt-controller

  - interrupts-extended



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: mips,p8700-aclint-sswi

    then:

      required:

        - riscv,hart-indexes

    else:

      properties:

        riscv,hart-indexes: false



examples:

  - |

    //Example 1

    interrupt-controller@94000000 {

      compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";

      reg = <0x94000000 0x00004000>;
@@ -55,4 +86,19 @@ examples: 
                            <&cpu3intc 1>,

                            <&cpu4intc 1>;

    };



  - |

    //Example 2

    interrupt-controller@94000000 {

      compatible = "mips,p8700-aclint-sswi";

      reg = <0x94000000 0x00004000>;

      #interrupt-cells = <0>;

      interrupt-controller;

      interrupts-extended = <&cpu1intc 1>,

                            <&cpu2intc 1>,

                            <&cpu3intc 1>,

                            <&cpu4intc 1>;

      riscv,hart-indexes = <0x0 0x1 0x10 0x11>;

    };



...