Commit ed9895d8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.7-2024-01-04' of... 

Merge tag 'amd-drm-fixes-6.7-2024-01-04' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amdgpu:
- DP MST fix
- SMU 13.0.6 fixes
- Fix displays on macbooks using vega12
- Fix VSC and colorimetry on DP/eDP

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240104152139.4931-1-alexander.deucher@amd.com
parents faa21f4c f71cee97

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −9
Original line number Diff line number Diff line
@@ -2188,15 +2188,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) 


	adev->firmware.gpu_info_fw = NULL;



	if (adev->mman.discovery_bin) {

		/*

		 * FIXME: The bounding box is still needed by Navi12, so

		 * temporarily read it from gpu_info firmware. Should be dropped

		 * when DAL no longer needs it.

		 */

		if (adev->asic_type != CHIP_NAVI12)

	if (adev->mman.discovery_bin)

		return 0;

	}



	switch (adev->asic_type) {

	default:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+6 −5
Original line number Diff line number Diff line
@@ -6170,8 +6170,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 


	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)

		mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);



	if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {

	else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||

			 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||

			 stream->signal == SIGNAL_TYPE_EDP) {

		//

		// should decide stream support vsc sdp colorimetry capability

		// before building vsc info packet
@@ -6187,8 +6188,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 
		if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)

			tf = TRANSFER_FUNC_GAMMA_22;

		mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);

		aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;



		if (stream->link->psr_settings.psr_feature_enabled)

			aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;

	}

finish:

	dc_sink_release(sink);
@@ -6914,7 +6916,6 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 
	if (IS_ERR(mst_state))

		return PTR_ERR(mst_state);



	if (!mst_state->pbn_div)

	mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);



	if (!state->duplicated) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+109 −1
Original line number Diff line number Diff line
@@ -440,7 +440,115 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = { 
	.use_urgent_burst_bw = 0

};



struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };

struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = {

	.clock_limits = {

		{

			.state = 0,

			.dcfclk_mhz = 560.0,

			.fabricclk_mhz = 560.0,

			.dispclk_mhz = 513.0,

			.dppclk_mhz = 513.0,

			.phyclk_mhz = 540.0,

			.socclk_mhz = 560.0,

			.dscclk_mhz = 171.0,

			.dram_speed_mts = 1069.0,

		},

		{

			.state = 1,

			.dcfclk_mhz = 694.0,

			.fabricclk_mhz = 694.0,

			.dispclk_mhz = 642.0,

			.dppclk_mhz = 642.0,

			.phyclk_mhz = 600.0,

			.socclk_mhz = 694.0,

			.dscclk_mhz = 214.0,

			.dram_speed_mts = 1324.0,

		},

		{

			.state = 2,

			.dcfclk_mhz = 875.0,

			.fabricclk_mhz = 875.0,

			.dispclk_mhz = 734.0,

			.dppclk_mhz = 734.0,

			.phyclk_mhz = 810.0,

			.socclk_mhz = 875.0,

			.dscclk_mhz = 245.0,

			.dram_speed_mts = 1670.0,

		},

		{

			.state = 3,

			.dcfclk_mhz = 1000.0,

			.fabricclk_mhz = 1000.0,

			.dispclk_mhz = 1100.0,

			.dppclk_mhz = 1100.0,

			.phyclk_mhz = 810.0,

			.socclk_mhz = 1000.0,

			.dscclk_mhz = 367.0,

			.dram_speed_mts = 2000.0,

		},

		{

			.state = 4,

			.dcfclk_mhz = 1200.0,

			.fabricclk_mhz = 1200.0,

			.dispclk_mhz = 1284.0,

			.dppclk_mhz = 1284.0,

			.phyclk_mhz = 810.0,

			.socclk_mhz = 1200.0,

			.dscclk_mhz = 428.0,

			.dram_speed_mts = 2000.0,

		},

		{

			.state = 5,

			.dcfclk_mhz = 1200.0,

			.fabricclk_mhz = 1200.0,

			.dispclk_mhz = 1284.0,

			.dppclk_mhz = 1284.0,

			.phyclk_mhz = 810.0,

			.socclk_mhz = 1200.0,

			.dscclk_mhz = 428.0,

			.dram_speed_mts = 2000.0,

		},

	},



	.num_states = 5,

	.sr_exit_time_us = 1.9,

	.sr_enter_plus_exit_time_us = 4.4,

	.urgent_latency_us = 3.0,

	.urgent_latency_pixel_data_only_us = 4.0,

	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,

	.urgent_latency_vm_data_only_us = 4.0,

	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,

	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,

	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,

	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,

	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,

	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,

	.max_avg_sdp_bw_use_normal_percent = 40.0,

	.max_avg_dram_bw_use_normal_percent = 40.0,

	.writeback_latency_us = 12.0,

	.ideal_dram_bw_after_urgent_percent = 40.0,

	.max_request_size_bytes = 256,

	.dram_channel_width_bytes = 16,

	.fabric_datapath_to_dcn_data_return_bytes = 64,

	.dcn_downspread_percent = 0.5,

	.downspread_percent = 0.5,

	.dram_page_open_time_ns = 50.0,

	.dram_rw_turnaround_time_ns = 17.5,

	.dram_return_buffer_per_channel_bytes = 8192,

	.round_trip_ping_latency_dcfclk_cycles = 131,

	.urgent_out_of_order_return_per_channel_bytes = 4096,

	.channel_interleave_bytes = 256,

	.num_banks = 8,

	.num_chans = 16,

	.vmm_page_size_bytes = 4096,

	.dram_clock_change_latency_us = 45.0,

	.writeback_dram_clock_change_latency_us = 23.0,

	.return_bus_width_bytes = 64,

	.dispclk_dppclk_vco_speed_mhz = 3850,

	.xfc_bus_transport_time_us = 20,

	.xfc_xbuf_latency_tolerance_us = 50,

	.use_urgent_burst_bw = 0,

};



struct _vcs_dpi_ip_params_st dcn2_1_ip = {

	.odm_capable = 1,

drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c

+8 −5
Original line number Diff line number Diff line
@@ -147,12 +147,15 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, 
	}



	/* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */

	if (stream->link->psr_settings.psr_feature_enabled) {

		if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)

			vsc_packet_revision = vsc_packet_rev4;

	else if (stream->link->replay_settings.config.replay_supported)

		vsc_packet_revision = vsc_packet_rev4;

		else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)

			vsc_packet_revision = vsc_packet_rev2;

	}



	if (stream->link->replay_settings.config.replay_supported)

		vsc_packet_revision = vsc_packet_rev4;



	/* Update to revision 5 for extended colorimetry support */

	if (stream->use_vsc_sdp_for_colorimetry)

drivers/gpu/drm/amd/include/kgd_pp_interface.h

+80 −0
Original line number Diff line number Diff line
@@ -318,6 +318,7 @@ enum pp_xgmi_plpd_mode { 
#define MAX_GFX_CLKS 8

#define MAX_CLKS 4

#define NUM_VCN 4

#define NUM_JPEG_ENG 32



struct seq_file;

enum amd_pp_clock_type;
@@ -774,6 +775,85 @@ struct gpu_metrics_v1_4 { 
	uint16_t			padding;

};



struct gpu_metrics_v1_5 {

	struct metrics_table_header	common_header;



	/* Temperature (Celsius) */

	uint16_t			temperature_hotspot;

	uint16_t			temperature_mem;

	uint16_t			temperature_vrsoc;



	/* Power (Watts) */

	uint16_t			curr_socket_power;



	/* Utilization (%) */

	uint16_t			average_gfx_activity;

	uint16_t			average_umc_activity; // memory controller

	uint16_t			vcn_activity[NUM_VCN];

	uint16_t			jpeg_activity[NUM_JPEG_ENG];



	/* Energy (15.259uJ (2^-16) units) */

	uint64_t			energy_accumulator;



	/* Driver attached timestamp (in ns) */

	uint64_t			system_clock_counter;



	/* Throttle status */

	uint32_t			throttle_status;



	/* Clock Lock Status. Each bit corresponds to clock instance */

	uint32_t			gfxclk_lock_status;



	/* Link width (number of lanes) and speed (in 0.1 GT/s) */

	uint16_t			pcie_link_width;

	uint16_t			pcie_link_speed;



	/* XGMI bus width and bitrate (in Gbps) */

	uint16_t			xgmi_link_width;

	uint16_t			xgmi_link_speed;



	/* Utilization Accumulated (%) */

	uint32_t			gfx_activity_acc;

	uint32_t			mem_activity_acc;



	/*PCIE accumulated bandwidth (GB/sec) */

	uint64_t			pcie_bandwidth_acc;



	/*PCIE instantaneous bandwidth (GB/sec) */

	uint64_t			pcie_bandwidth_inst;



	/* PCIE L0 to recovery state transition accumulated count */

	uint64_t			pcie_l0_to_recov_count_acc;



	/* PCIE replay accumulated count */

	uint64_t			pcie_replay_count_acc;



	/* PCIE replay rollover accumulated count */

	uint64_t			pcie_replay_rover_count_acc;



	/* PCIE NAK sent  accumulated count */

	uint32_t			pcie_nak_sent_count_acc;



	/* PCIE NAK received accumulated count */

	uint32_t			pcie_nak_rcvd_count_acc;



	/* XGMI accumulated data transfer size(KiloBytes) */

	uint64_t			xgmi_read_data_acc[NUM_XGMI_LINKS];

	uint64_t			xgmi_write_data_acc[NUM_XGMI_LINKS];



	/* PMFW attached timestamp (10ns resolution) */

	uint64_t			firmware_timestamp;



	/* Current clocks (Mhz) */

	uint16_t			current_gfxclk[MAX_GFX_CLKS];

	uint16_t			current_socclk[MAX_CLKS];

	uint16_t			current_vclk0[MAX_CLKS];

	uint16_t			current_dclk0[MAX_CLKS];

	uint16_t			current_uclk;



	uint16_t			padding;

};



/*

 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.

 * Use gpu_metrics_v2_1 or later instead.