Commit edbbae7f authored by Marco Felsch's avatar Marco Felsch Committed by Shawn Guo
Browse files

ARM: dts: imx7: add MIPI-DSI support 



This adds the device tree support for the MIPI-DSI block. The block can
be used as encoder for the parallel signals coming from the lcdif block.

Signed-off-by: default avatarMarco Felsch <m.felsch@pengutronix.de>
Signed-off-by: default avatarRoland Hieber <rhi@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 0b6b2650

arch/arm/boot/dts/nxp/imx/imx7s.dtsi

+46 −0
Original line number Diff line number Diff line
@@ -825,6 +825,16 @@ lcdif: lcdif@30730000 { 
					<&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;

				clock-names = "pix", "axi";

				status = "disabled";



				port {

					#address-cells = <1>;

					#size-cells = <0>;



					lcdif_out_mipi_dsi: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&mipi_dsi_in_lcdif>;

					};

				};

			};



			mipi_csi: mipi-csi@30750000 {
@@ -857,6 +867,42 @@ mipi_vc0_to_csi_mux: endpoint { 
					};

				};

			};



			mipi_dsi: dsi@30760000 {

				compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim";

				#address-cells = <1>;

				#size-cells = <0>;

				reg = <0x30760000 0x400>;

				clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,

					 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;

				clock-names = "bus_clk", "sclk_mipi";

				assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>,

						  <&clks IMX7D_PLL_SYS_PFD5_CLK>;

				assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>;

				assigned-clock-rates = <0>, <333000000>;

				power-domains = <&pgc_mipi_phy>;

				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

				samsung,burst-clock-frequency = <891000000>;

				samsung,esc-clock-frequency = <20000000>;

				samsung,pll-clock-frequency = <24000000>;

				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						#address-cells = <1>;

						#size-cells = <0>;



						mipi_dsi_in_lcdif: endpoint@0 {

							reg = <0>;

							remote-endpoint = <&lcdif_out_mipi_dsi>;

						};

					};

				};

			};

		};



		aips3: bus@30800000 {