Commit eddc8a05 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/dmc: Parametrize MTL_PIPEDMC_GATING_DIS 



The MTL+ pipe DMC clock gating bits can be parametrized.
Make it so.

Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-3-ville.syrjala@linux.intel.com
parent 42a7bf8a

drivers/gpu/drm/i915/display/intel_dmc.c

+2 −1
Original line number Diff line number Diff line
@@ -483,7 +483,8 @@ static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 
	 * for pipe A and B.

	 */

	intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,

		     MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);

		     MTL_PIPEDMC_GATING_DIS(PIPE_A) |

		     MTL_PIPEDMC_GATING_DIS(PIPE_B));

}



static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/i915_reg.h

+1 −2
Original line number Diff line number Diff line
@@ -763,8 +763,7 @@ 
 */

#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)

#define   DARBF_GATING_DIS		REG_BIT(27)

#define   MTL_PIPEDMC_GATING_DIS_A	REG_BIT(15)

#define   MTL_PIPEDMC_GATING_DIS_B	REG_BIT(14)

#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))

#define   PWM2_GATING_DIS		REG_BIT(14)

#define   PWM1_GATING_DIS		REG_BIT(13)