Commit ee316213 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2025-11-18' of https://gitlab.freedesktop.org/drm/msm into drm-next 



Changes for v6.19:

GPU:
- Gen8 support: A840 (Kaanapali) and X2-85 (Glymur)
- A612 support
- A few NULL check fixes

MDSS:
- Added support for Glymur and QCS8300 platforms

DPU:
- Enabled Quad-Pipe support, unlocking higher resolutions support
- Added support for Glymur platform
- Documented DPU on QCS8300 platform as supported
- Misc small fixes

DisplayPort:
- Added support for Glymur platform
- Added support lame remapping inside DP block
- Documented DisplayPort controller on QCS8300 and SM6150/QCS615 as
  supported

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://patch.msgid.link/CACSVV00sFi65XrZipHCU3C0bYji7vgu7OgWvLeOQ1Cg475_pUA@mail.gmail.com
parents ce0478b0 7bc29d5f

Documentation/devicetree/bindings/display/msm/dp-controller.yaml

+16 −1
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ properties: 
  compatible:

    oneOf:

      - enum:

          - qcom,glymur-dp

          - qcom,sa8775p-dp

          - qcom,sc7180-dp

          - qcom,sc7280-dp
@@ -31,6 +32,11 @@ properties: 
          - qcom,sm8650-dp

          - qcom,x1e80100-dp



      - items:

          - enum:

              - qcom,qcs8300-dp

          - const: qcom,sa8775p-dp



      - items:

          - enum:

              - qcom,sm6350-dp
@@ -53,6 +59,12 @@ properties: 
              - qcom,sm8550-dp

          - const: qcom,sm8350-dp



      - items:

          - enum:

              - qcom,sm6150-dp

          - const: qcom,sm8150-dp

          - const: qcom,sm8350-dp



      - items:

          - enum:

              - qcom,sm8750-dp
@@ -195,9 +207,11 @@ allOf: 
          compatible:

            contains:

              enum:

                - qcom,glymur-dp

                - qcom,sa8775p-dp

                - qcom,x1e80100-dp

      then:

        $ref: /schemas/sound/dai-common.yaml#

        oneOf:

          - required:

              - aux-bus
@@ -239,6 +253,7 @@ allOf: 
            enum:

              # these platforms support 2 streams MST on some interfaces,

              # others are SST only

              - qcom,glymur-dp

              - qcom,sc8280xp-dp

              - qcom,x1e80100-dp

    then:
@@ -295,7 +310,7 @@ allOf: 
          minItems: 6

          maxItems: 8



additionalProperties: false

unevaluatedProperties: false



examples:

  - |

Documentation/devicetree/bindings/display/msm/gmu.yaml

+59 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ properties: 
  compatible:

    oneOf:

      - items:

          - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'

          - pattern: '^qcom,adreno-gmu-[6-8][0-9][0-9]\.[0-9]$'

          - const: qcom,adreno-gmu

      - items:

          - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
@@ -299,6 +299,64 @@ allOf: 
      required:

        - qcom,qmp



  - if:

      properties:

        compatible:

          contains:

            const: qcom,adreno-gmu-840.1

    then:

      properties:

        reg:

          items:

            - description: Core GMU registers

        reg-names:

          items:

            - const: gmu

        clocks:

          items:

            - description: GPU AHB clock

            - description: GMU clock

            - description: GPU CX clock

            - description: GPU MEMNOC clock

            - description: GMU HUB clock

        clock-names:

          items:

            - const: ahb

            - const: gmu

            - const: cxo

            - const: memnoc

            - const: hub



  - if:

      properties:

        compatible:

          contains:

            const: qcom,adreno-gmu-x285.1

    then:

      properties:

        reg:

          items:

            - description: Core GMU registers

        reg-names:

          items:

            - const: gmu

        clocks:

          items:

            - description: GPU AHB clock

            - description: GMU clock

            - description: GPU CX clock

            - description: GPU MEMNOC clock

            - description: GMU HUB clock

            - description: GMU RSCC HUB clock

        clock-names:

          items:

            - const: ahb

            - const: gmu

            - const: cxo

            - const: memnoc

            - const: hub

            - const: rscc



  - if:

      properties:

        compatible:

Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml

0 → 100644
+264 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,glymur-mdss.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Glymur Display MDSS



maintainers:

  - Abel Vesa <abel.vesa@linaro.org>



description:

  Glymur MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like

  DPU display controller, DP interfaces, etc.



$ref: /schemas/display/msm/mdss-common.yaml#



properties:

  compatible:

    const: qcom,glymur-mdss



  clocks:

    items:

      - description: Display AHB

      - description: Display hf AXI

      - description: Display core



  iommus:

    maxItems: 1



  interconnects:

    items:

      - description: Interconnect path from mdp0 port to the data bus

      - description: Interconnect path from CPU to the reg bus



  interconnect-names:

    items:

      - const: mdp0-mem

      - const: cpu-cfg



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        const: qcom,glymur-dpu



  "^displayport-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        const: qcom,glymur-dp



  "^phy@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        const: qcom,glymur-dp-phy



required:

  - compatible



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/interconnect/qcom,icc.h>

    #include <dt-bindings/interconnect/qcom,glymur-rpmh.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/phy/phy-qcom-qmp.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>



    display-subsystem@ae00000 {

            compatible = "qcom,glymur-mdss";

            reg = <0x0ae00000 0x1000>;

            reg-names = "mdss";



            interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;



            clocks = <&dispcc_ahb_clk>,

                     <&gcc_disp_hf_axi_clk>,

                     <&dispcc_mdp_clk>;

            clock-names = "bus", "nrt_bus", "core";



            interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS

                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

                            <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY

                             &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;

            interconnect-names = "mdp0-mem",

                                 "cpu-cfg";



            resets = <&disp_cc_mdss_core_bcr>;



            power-domains = <&mdss_gdsc>;



            iommus = <&apps_smmu 0x1c00 0x2>;



            interrupt-controller;

            #interrupt-cells = <1>;



            #address-cells = <1>;

            #size-cells = <1>;

            ranges;



            display-controller@ae01000 {

                compatible = "qcom,glymur-dpu";

                reg = <0x0ae01000 0x8f000>,

                      <0x0aeb0000 0x2008>;

                reg-names = "mdp", "vbif";



                clocks = <&gcc_axi_clk>,

                         <&dispcc_ahb_clk>,

                         <&dispcc_mdp_lut_clk>,

                         <&dispcc_mdp_clk>,

                         <&dispcc_mdp_vsync_clk>;

                clock-names = "nrt_bus",

                              "iface",

                              "lut",

                              "core",

                              "vsync";



                assigned-clocks = <&dispcc_mdp_vsync_clk>;

                assigned-clock-rates = <19200000>;



                operating-points-v2 = <&mdp_opp_table>;

                power-domains = <&rpmhpd RPMHPD_MMCX>;



                interrupt-parent = <&mdss>;

                interrupts = <0>;



                ports {

                    #address-cells = <1>;

                    #size-cells = <0>;



                    port@0 {

                        reg = <0>;

                        dpu_intf1_out: endpoint {

                            remote-endpoint = <&dsi0_in>;

                        };

                    };



                    port@1 {

                        reg = <1>;

                        dpu_intf2_out: endpoint {

                            remote-endpoint = <&dsi1_in>;

                        };

                    };

                };



                mdp_opp_table: opp-table {

                    compatible = "operating-points-v2";



                    opp-200000000 {

                        opp-hz = /bits/ 64 <200000000>;

                        required-opps = <&rpmhpd_opp_low_svs>;

                    };



                    opp-325000000 {

                        opp-hz = /bits/ 64 <325000000>;

                        required-opps = <&rpmhpd_opp_svs>;

                    };



                    opp-375000000 {

                        opp-hz = /bits/ 64 <375000000>;

                        required-opps = <&rpmhpd_opp_svs_l1>;

                    };



                    opp-514000000 {

                        opp-hz = /bits/ 64 <514000000>;

                        required-opps = <&rpmhpd_opp_nom>;

                    };

                };

            };



            displayport-controller@ae90000 {

                compatible = "qcom,glymur-dp";

                reg = <0xae90000 0x200>,

                      <0xae90200 0x200>,

                      <0xae90400 0x600>,

                      <0xae91000 0x400>,

                      <0xae91400 0x400>;



                interrupt-parent = <&mdss>;

                interrupts = <12>;



                clocks = <&dispcc_mdss_ahb_clk>,

                         <&dispcc_dptx0_aux_clk>,

                         <&dispcc_dptx0_link_clk>,

                         <&dispcc_dptx0_link_intf_clk>,

                         <&dispcc_dptx0_pixel0_clk>,

                         <&dispcc_dptx0_pixel1_clk>;

                clock-names = "core_iface",

                              "core_aux",

                              "ctrl_link",

                              "ctrl_link_iface",

                              "stream_pixel",

                              "stream_1_pixel";



                assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,

                                  <&dispcc_mdss_dptx0_pixel0_clk_src>,

                                  <&dispcc_mdss_dptx0_pixel1_clk_src>;

                assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,

                                         <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,

                                         <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;



                operating-points-v2 = <&mdss_dp0_opp_table>;



                power-domains = <&rpmhpd RPMHPD_MMCX>;



                phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;

                phy-names = "dp";



                #sound-dai-cells = <0>;



                ports {

                    #address-cells = <1>;

                    #size-cells = <0>;



                    port@0 {

                        reg = <0>;



                        mdss_dp0_in: endpoint {

                          remote-endpoint = <&mdss_intf0_out>;

                        };

                    };



                    port@1 {

                        reg = <1>;



                        mdss_dp0_out: endpoint {

                        };

                    };

                };



                mdss_dp0_opp_table: opp-table {

                    compatible = "operating-points-v2";



                    opp-160000000 {

                        opp-hz = /bits/ 64 <160000000>;

                        required-opps = <&rpmhpd_opp_low_svs>;

                    };



                    opp-270000000 {

                        opp-hz = /bits/ 64 <270000000>;

                        required-opps = <&rpmhpd_opp_svs>;

                    };



                    opp-540000000 {

                        opp-hz = /bits/ 64 <540000000>;

                        required-opps = <&rpmhpd_opp_svs_l1>;

                    };



                    opp-810000000 {

                        opp-hz = /bits/ 64 <810000000>;

                        required-opps = <&rpmhpd_opp_nom>;

                    };

                };

            };

        };

...

Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml

0 → 100644
+286 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,qcs8300-mdss.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Technologies, Inc. QCS8300 Display MDSS



maintainers:

  - Yongxing Mou <yongxing.mou@oss.qualcomm.com>



description:

  QCS8300 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like

  DPU display controller, DP interfaces and EDP etc.



$ref: /schemas/display/msm/mdss-common.yaml#



properties:

  compatible:

    const: qcom,qcs8300-mdss



  clocks:

    items:

      - description: Display AHB

      - description: Display hf AXI

      - description: Display core



  iommus:

    maxItems: 1



  interconnects:

    maxItems: 3



  interconnect-names:

    maxItems: 3



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true



    properties:

      compatible:

        contains:

          const: qcom,qcs8300-dpu



  "^displayport-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true



    properties:

      compatible:

        contains:

          const: qcom,qcs8300-dp



  "^phy@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        contains:

          const: qcom,qcs8300-edp-phy



required:

  - compatible



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interconnect/qcom,icc.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/qcom,qcs8300-gcc.h>

    #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>

    #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    mdss: display-subsystem@ae00000 {

        compatible = "qcom,qcs8300-mdss";

        reg = <0x0ae00000 0x1000>;

        reg-names = "mdss";



        interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY

                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,

                        <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY

                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,

                        <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY

                         &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;

        interconnect-names = "mdp0-mem",

                             "mdp1-mem",

                             "cpu-cfg";



        resets = <&dispcc_core_bcr>;

        power-domains = <&dispcc_gdsc>;



        clocks = <&dispcc_ahb_clk>,

                 <&gcc GCC_DISP_HF_AXI_CLK>,

                 <&dispcc_mdp_clk>;



        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;

        #interrupt-cells = <1>;



        iommus = <&apps_smmu 0x1000 0x402>;



        #address-cells = <1>;

        #size-cells = <1>;

        ranges;



        display-controller@ae01000 {

            compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu";

            reg = <0x0ae01000 0x8f000>,

                  <0x0aeb0000 0x2008>;

            reg-names = "mdp", "vbif";



            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;

            clock-names = "nrt_bus",

                          "iface",

                          "lut",

                          "core",

                          "vsync";



            assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;

            assigned-clock-rates = <19200000>;

            operating-points-v2 = <&mdp_opp_table>;

            power-domains = <&rpmhpd RPMHPD_MMCX>;



            interrupt-parent = <&mdss>;

            interrupts = <0>;

            ports {

                #address-cells = <1>;

                #size-cells = <0>;

                port@0 {

                    reg = <0>;



                    dpu_intf0_out: endpoint {

                         remote-endpoint = <&mdss_dp0_in>;

                    };

                };

            };



            mdp_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-375000000 {

                    opp-hz = /bits/ 64 <375000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };



                opp-500000000 {

                    opp-hz = /bits/ 64 <500000000>;

                    required-opps = <&rpmhpd_opp_nom>;

                };



                opp-575000000 {

                    opp-hz = /bits/ 64 <575000000>;

                    required-opps = <&rpmhpd_opp_turbo>;

                };



                opp-650000000 {

                    opp-hz = /bits/ 64 <650000000>;

                    required-opps = <&rpmhpd_opp_turbo_l1>;

                };

            };

        };



        mdss_dp0_phy: phy@aec2a00 {

            compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";



            reg = <0x0aec2a00 0x200>,

                  <0x0aec2200 0xd0>,

                  <0x0aec2600 0xd0>,

                  <0x0aec2000 0x1c8>;



            clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,

                     <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;

            clock-names = "aux",

                          "cfg_ahb";



            #clock-cells = <1>;

            #phy-cells = <0>;



            vdda-phy-supply = <&vreg_l1c>;

            vdda-pll-supply = <&vreg_l4a>;

        };



        displayport-controller@af54000 {

            compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp";



            pinctrl-0 = <&dp_hot_plug_det>;

            pinctrl-names = "default";



            reg = <0xaf54000 0x104>,

                  <0xaf54200 0x0c0>,

                  <0xaf55000 0x770>,

                  <0xaf56000 0x09c>,

                  <0xaf57000 0x09c>,

                  <0xaf58000 0x09c>,

                  <0xaf59000 0x09c>,

                  <0xaf5a000 0x23c>,

                  <0xaf5b000 0x23c>;



            interrupt-parent = <&mdss>;

            interrupts = <12>;

            clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,

                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;

            clock-names = "core_iface",

                          "core_aux",

                          "ctrl_link",

                          "ctrl_link_iface",

                          "stream_pixel",

                          "stream_1_pixel",

                          "stream_2_pixel",

                          "stream_3_pixel";

            assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,

                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,

                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,

                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,

                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;

            assigned-clock-parents = <&mdss_dp0_phy 0>,

                                     <&mdss_dp0_phy 1>,

                                     <&mdss_dp0_phy 1>,

                                     <&mdss_dp0_phy 1>;

            phys = <&mdss_dp0_phy>;

            phy-names = "dp";

            operating-points-v2 = <&dp_opp_table>;

            power-domains = <&rpmhpd RPMHPD_MMCX>;



            #sound-dai-cells = <0>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;



                    mdss_dp0_in: endpoint {

                        remote-endpoint = <&dpu_intf0_out>;

                    };

                };



                port@1 {

                   reg = <1>;



                   mdss_dp_out: endpoint { };

                };

            };



            dp_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-160000000 {

                    opp-hz = /bits/ 64 <160000000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-270000000 {

                    opp-hz = /bits/ 64 <270000000>;

                    required-opps = <&rpmhpd_opp_svs>;

                };



                opp-540000000 {

                    opp-hz = /bits/ 64 <540000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };



                opp-810000000 {

                    opp-hz = /bits/ 64 <810000000>;

                    required-opps = <&rpmhpd_opp_nom>;

                };

            };

        };

    };

...

Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml

+25 −15
Original line number Diff line number Diff line
@@ -51,6 +51,14 @@ patternProperties: 
      compatible:

        const: qcom,sm6150-dpu



  "^displayport-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        contains:

          const: qcom,sm6150-dp



  "^dsi@[0-9a-f]+$":

    type: object

    additionalProperties: true
@@ -131,12 +139,14 @@ examples: 


                port@0 {

                    reg = <0>;



                    dpu_intf0_out: endpoint {

                    };

                };



                port@1 {

                    reg = <1>;



                    dpu_intf1_out: endpoint {

                        remote-endpoint = <&mdss_dsi0_in>;

                    };
@@ -146,13 +156,13 @@ examples: 
            mdp_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-19200000 {

                  opp-hz = /bits/ 64 <19200000>;

                opp-192000000 {

                    opp-hz = /bits/ 64 <192000000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-25600000 {

                  opp-hz = /bits/ 64 <25600000>;

                opp-256000000 {

                    opp-hz = /bits/ 64 <256000000>;

                    required-opps = <&rpmhpd_opp_svs>;

                };