Commit ee3f54cf authored by Tinghan Shen's avatar Tinghan Shen Committed by Matthias Brugger
Browse files
parent c4f85939
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+24 −0
Original line number Diff line number Diff line
@@ -1962,6 +1962,30 @@ larb19: larb@1a010000 {
			power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
		};

		venc: video-codec@1a020000 {
			compatible = "mediatek,mt8195-vcodec-enc";
			reg = <0 0x1a020000 0 0x10000>;
			iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
				 <&iommu_vdo M4U_PORT_L19_VENC_REC>,
				 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
				 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
				 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
				 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
				 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
				 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
				 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
			mediatek,scp = <&scp>;
			clocks = <&vencsys CLK_VENC_VENC>;
			clock-names = "venc_sel";
			assigned-clocks = <&topckgen CLK_TOP_VENC>;
			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
			power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
			#address-cells = <2>;
			#size-cells = <2>;
			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
		};

		vencsys_core1: clock-controller@1b000000 {
			compatible = "mediatek,mt8195-vencsys_core1";
			reg = <0 0x1b000000 0 0x1000>;