Commit ee462455 authored by Thorsten Blum's avatar Thorsten Blum Committed by Dinh Nguyen
Browse files

clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate() 



Since readl() returns a u32, the local variable reg can also have the
data type u32. Furthermore, divf and divq are derived from reg and can
also be a u32.

Since do_div() casts the divisor to u32 anyway, changing the data type
of divq to u32 also removes the following Coccinelle/coccicheck warning
reported by do_div.cocci:

  WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead

Compile-tested only.

Signed-off-by: default avatarThorsten Blum <thorsten.blum@linux.dev>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 40384c84

drivers/clk/socfpga/clk-pll-a10.c

+1 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, 
					 unsigned long parent_rate)

{

	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);

	unsigned long divf, divq, reg;

	u32 divf, divq, reg;

	unsigned long long vco_freq;



	/* read VCO1 reg for numerator and denominator */