Unverified Commit ee7dad0b authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'riscv-dt-for-v6.9' of... 

Merge tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

 into soc/late

RISC-V Devicetrees for v6.9

Microchip:
Missing bus clocks for the CAN controllers spotted during the creation
of a driver for the controllers and a specific compatible for the SiFive
PDMA block on PolarFire SoC.

Starfive:
PWM nodes for the jh7100 and jh7110. Camera subsystem support for the
latter. Most notably however is the addition of ethernet support for the
jh7110 which finally allows people to use the network on the OG VisionFive
and on the Beagle-V Starlight board. This was made possible by the
non-standard cache management operations support added for the RZ/Five
which could be extended to the ccache present on the jh7100.

bindings:
Additional clarification for what the reg property represents for cpus
and two opencores PWM binding changes - the original addition and an
added compatible. The latter is here as the driver patch was not ready
but the PWM maintainer told me to go ahead and merge it.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: jh7110: Add camera subsystem nodes
  dt-bindings: pwm: opencores: Add compatible for StarFive JH8100
  dt-bindings: riscv: cpus: reg matches hart ID
  riscv: dts: microchip: add specific compatible for mpfs pdma
  riscv: dts: microchip: add missing CAN bus clocks
  riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio
  riscv: dts: starfive: visionfive-v1: Setup ethernet phy
  riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac
  riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes
  riscv: dts: starfive: jh7110: Add PWM node and pins configuration
  riscv: dts: starfive: jh7100: Add PWM node and pins configuration
  dt-bindings: pwm: Add bindings for OpenCores PWM Controller

Link: https://lore.kernel.org/r/20240305-iodine-moneywise-53797ae9bf6e@spud


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 724ad89f 28ecaaa5

Documentation/devicetree/bindings/pwm/opencores,pwm.yaml

0 → 100644
+56 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: OpenCores PWM controller



maintainers:

  - William Qiu <william.qiu@starfivetech.com>



description:

  The OpenCores PTC ip core contains a PWM controller. When operating in PWM

  mode, the PTC core generates binary signal with user-programmable low and

  high periods. All PTC counters and registers are 32-bit.



allOf:

  - $ref: pwm.yaml#



properties:

  compatible:

    items:

      - enum:

          - starfive,jh7100-pwm

          - starfive,jh7110-pwm

          - starfive,jh8100-pwm

      - const: opencores,pwm-v1



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  resets:

    maxItems: 1



  "#pwm-cells":

    const: 3



required:

  - compatible

  - reg

  - clocks



additionalProperties: false



examples:

  - |

    pwm@12490000 {

        compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";

        reg = <0x12490000 0x10000>;

        clocks = <&clkgen 181>;

        resets = <&rstgen 109>;

        #pwm-cells = <3>;

    };

Documentation/devicetree/bindings/riscv/cpus.yaml

+4 −0
Original line number Diff line number Diff line
@@ -75,6 +75,10 @@ properties: 
      - riscv,sv57

      - riscv,none



  reg:

    description:

      The hart ID of this CPU node.



  riscv,cbom-block-size:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

arch/riscv/boot/dts/microchip/mpfs.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -243,7 +243,7 @@ plic: interrupt-controller@c000000 { 
		};



		pdma: dma-controller@3000000 {

			compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";

			compatible = "microchip,mpfs-pdma", "sifive,pdma0";

			reg = <0x0 0x3000000 0x0 0x8000>;

			interrupt-parent = <&plic>;

			interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
@@ -422,7 +422,7 @@ i2c1: i2c@2010b000 { 
		can0: can@2010c000 {

			compatible = "microchip,mpfs-can";

			reg = <0x0 0x2010c000 0x0 0x1000>;

			clocks = <&clkcfg CLK_CAN0>;

			clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;

			interrupt-parent = <&plic>;

			interrupts = <56>;

			status = "disabled";
@@ -431,7 +431,7 @@ can0: can@2010c000 { 
		can1: can@2010d000 {

			compatible = "microchip,mpfs-can";

			reg = <0x0 0x2010d000 0x0 0x1000>;

			clocks = <&clkcfg CLK_CAN1>;

			clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;

			interrupt-parent = <&plic>;

			interrupts = <57>;

			status = "disabled";

arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts

+11 −0
Original line number Diff line number Diff line
@@ -11,3 +11,14 @@ / { 
	model = "BeagleV Starlight Beta";

	compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";

};



&gmac {

	phy-handle = <&phy>;

};



&mdio {

	phy: ethernet-phy@7 {

		reg = <7>;

		reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;

	};

};

arch/riscv/boot/dts/starfive/jh7100-common.dtsi

+108 −0
Original line number Diff line number Diff line
@@ -72,7 +72,91 @@ wifi_pwrseq: wifi-pwrseq { 
	};

};



&gmac {

	pinctrl-names = "default";

	pinctrl-0 = <&gmac_pins>;

	phy-mode = "rgmii-id";

	status = "okay";



	mdio: mdio {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "snps,dwmac-mdio";

	};

};



&gpio {

	gmac_pins: gmac-0 {

		gtxclk-pins {

			pins = <PAD_FUNC_SHARE(115)>;

			bias-pull-up;

			drive-strength = <35>;

			input-enable;

			input-schmitt-enable;

			slew-rate = <0>;

		};

		miitxclk-pins {

			pins = <PAD_FUNC_SHARE(116)>;

			bias-pull-up;

			drive-strength = <14>;

			input-enable;

			input-schmitt-disable;

			slew-rate = <0>;

		};

		tx-pins {

			pins = <PAD_FUNC_SHARE(117)>,

			       <PAD_FUNC_SHARE(119)>,

			       <PAD_FUNC_SHARE(120)>,

			       <PAD_FUNC_SHARE(121)>,

			       <PAD_FUNC_SHARE(122)>,

			       <PAD_FUNC_SHARE(123)>,

			       <PAD_FUNC_SHARE(124)>,

			       <PAD_FUNC_SHARE(125)>,

			       <PAD_FUNC_SHARE(126)>;

			bias-pull-up;

			drive-strength = <35>;

			input-disable;

			input-schmitt-disable;

			slew-rate = <0>;

		};

		rxclk-pins {

			pins = <PAD_FUNC_SHARE(127)>;

			bias-pull-up;

			drive-strength = <14>;

			input-enable;

			input-schmitt-disable;

			slew-rate = <6>;

		};

		rxer-pins {

			pins = <PAD_FUNC_SHARE(129)>;

			bias-pull-up;

			drive-strength = <14>;

			input-enable;

			input-schmitt-disable;

			slew-rate = <0>;

		};

		rx-pins {

			pins = <PAD_FUNC_SHARE(128)>,

			       <PAD_FUNC_SHARE(130)>,

			       <PAD_FUNC_SHARE(131)>,

			       <PAD_FUNC_SHARE(132)>,

			       <PAD_FUNC_SHARE(133)>,

			       <PAD_FUNC_SHARE(134)>,

			       <PAD_FUNC_SHARE(135)>,

			       <PAD_FUNC_SHARE(136)>,

			       <PAD_FUNC_SHARE(137)>,

			       <PAD_FUNC_SHARE(138)>,

			       <PAD_FUNC_SHARE(139)>,

			       <PAD_FUNC_SHARE(140)>,

			       <PAD_FUNC_SHARE(141)>;

			bias-pull-up;

			drive-strength = <14>;

			input-enable;

			input-schmitt-enable;

			slew-rate = <0>;

		};

	};



	i2c0_pins: i2c0-0 {

		i2c-pins {

			pinmux = <GPIOMUX(62, GPO_LOW,
@@ -115,6 +199,24 @@ GPO_I2C2_PAD_SDA_OEN, 
		};

	};



	pwm_pins: pwm-0 {

		pwm-pins {

			pinmux = <GPIOMUX(7,

				  GPO_PWM_PAD_OUT_BIT0,

				  GPO_PWM_PAD_OE_N_BIT0,

				  GPI_NONE)>,

				 <GPIOMUX(5,

				  GPO_PWM_PAD_OUT_BIT1,

				  GPO_PWM_PAD_OE_N_BIT1,

				  GPI_NONE)>;

			bias-disable;

			drive-strength = <35>;

			input-disable;

			input-schmitt-disable;

			slew-rate = <0>;

		};

	};



	sdio0_pins: sdio0-0 {

		clk-pins {

			pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
@@ -257,6 +359,12 @@ &osc_aud { 
	clock-frequency = <27000000>;

};



&pwm {

	pinctrl-names = "default";

	pinctrl-0 = <&pwm_pins>;

	status = "okay";

};



&sdio0 {

	broken-cd;

	bus-width = <4>;