Commit eea4f89b authored by Tomi Valkeinen's avatar Tomi Valkeinen
Browse files

drm/bridge: cdns-dsi: Fix REG_WAKEUP_TIME value 



The driver tries to calculate the value for REG_WAKEUP_TIME. However,
the calculation itself is not correct, and to add on it, the resulting
value is almost always larger than the field's size, so the actual
result is more or less random.

According to the docs, figuring out the value for REG_WAKEUP_TIME
requires HW characterization and there's no way to have a generic
algorithm to come up with the value. That doesn't help at all...

However, we know that the value must be smaller than the line time, and,
at least in my understanding, the proper value for it is quite small.
Testing shows that setting it to 1/10 of the line time seems to work
well. All video modes from my HDMI monitor work with this algorithm.

Hopefully we'll get more information on how to calculate the value, and
we can then update this.

Tested-by: default avatarParth Pancholi <parth.pancholi@toradex.com>
Tested-by: default avatarJayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: default avatarDevarsh Thakkar <devarsht@ti.com>
Link: https://lore.kernel.org/r/20250723-cdns-dsi-impro-v5-11-e61cc06074c2@ideasonboard.com


Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ideasonboard.com>
parent e948bcaf

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+7 −1
Original line number Diff line number Diff line
@@ -793,7 +793,13 @@ static void cdns_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 


	tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8,

					    phy_cfg->hs_clk_rate);

	reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / tx_byte_period;



	/*

	 * Estimated time [in clock cycles] to perform LP->HS on D-PHY.

	 * It is not clear how to calculate this, so for now,

	 * set it to 1/10 of the total number of clocks in a line.

	 */

	reg_wakeup = dsi_cfg.htotal / nlanes / 10;

	writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp),

	       dsi->regs + VID_DPHY_TIME);