Commit eec91e22 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-updates-v6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux 

Pull iommu updates from Joerg Roedel:
 "Core changes:
   - Allow ATS on VF when parent device is identity mapped
   - Optimize unmap path on ARM io-pagetable implementation
   - Use of_property_present()

  ARM-SMMU changes:
   - SMMUv2:
       - Devicetree binding updates for Qualcomm MMU-500 implementations
       - Extend workarounds for broken Qualcomm hypervisor to avoid
         touching features that are not available (e.g. 16KiB page
         support, reserved context banks)
   - SMMUv3:
       - Support for NVIDIA's custom virtual command queue hardware
       - Fix Stage-2 stall configuration and extend tests to cover this
         area
       - A bunch of driver cleanups, including simplification of the
         master rbtree code
   - Minor cleanups and fixes across both drivers

  Intel VT-d changes:
   - Retire si_domain and convert to use static identity domain
   - Batched IOTLB/dev-IOTLB invalidation
   - Small code refactoring and cleanups

  AMD-Vi changes:
   - Cleanup and refactoring of io-pagetable code
   - Add parameter to limit the used io-pagesizes
   - Other cleanups and fixes"

* tag 'iommu-updates-v6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (77 commits)
  dt-bindings: arm-smmu: Add compatible for QCS8300 SoC
  iommu/amd: Test for PAGING domains before freeing a domain
  iommu/amd: Fix argument order in amd_iommu_dev_flush_pasid_all()
  iommu/amd: Add kernel parameters to limit V1 page-sizes
  iommu/arm-smmu-v3: Reorganize struct arm_smmu_ctx_desc_cfg
  iommu/arm-smmu-v3: Add types for each level of the CD table
  iommu/arm-smmu-v3: Shrink the cdtab l1_desc array
  iommu/arm-smmu-v3: Do not use devm for the cd table allocations
  iommu/arm-smmu-v3: Remove strtab_base/cfg
  iommu/arm-smmu-v3: Reorganize struct arm_smmu_strtab_cfg
  iommu/arm-smmu-v3: Add types for each level of the 2 level stream table
  iommu/arm-smmu-v3: Add arm_smmu_strtab_l1/2_idx()
  iommu/arm-smmu-qcom: apply num_context_bank fixes for SDM630 / SDM660
  iommu/arm-smmu-v3: Use the new rb tree helpers
  dt-bindings: arm-smmu: document the support on SA8255p
  iommu/tegra241-cmdqv: Do not allocate vcmdq until dma_set_mask_and_coherent
  iommu/tegra241-cmdqv: Drop static at local variable
  iommu/tegra241-cmdqv: Fix ioremap() error handling in probe()
  iommu/amd: Do not set the D bit on AMD v2 table entries
  iommu/amd: Correct the reported page sizes from the V1 table
  ...
parents c27ea952 97162f60

Documentation/admin-guide/kernel-parameters.txt

+11 −6
Original line number Diff line number Diff line
@@ -339,6 +339,11 @@ 
			pgtbl_v1        - Use v1 page table for DMA-API (Default).

			pgtbl_v2        - Use v2 page table for DMA-API.

			irtcachedis     - Disable Interrupt Remapping Table (IRT) caching.

			nohugepages     - Limit page-sizes used for v1 page-tables

				          to 4 KiB.

			v2_pgsizes_only - Limit page-sizes used for v1 page-tables

				          to 4KiB/2Mib/1GiB.





	amd_iommu_dump=	[HW,X86-64]

			Enable AMD IOMMU driver option to dump the ACPI table

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

+5 −0
Original line number Diff line number Diff line
@@ -36,7 +36,9 @@ properties: 
        items:

          - enum:

              - qcom,qcm2290-smmu-500

              - qcom,qcs8300-smmu-500

              - qcom,qdu1000-smmu-500

              - qcom,sa8255p-smmu-500

              - qcom,sa8775p-smmu-500

              - qcom,sc7180-smmu-500

              - qcom,sc7280-smmu-500
@@ -84,6 +86,7 @@ properties: 
        items:

          - enum:

              - qcom,qcm2290-smmu-500

              - qcom,sa8255p-smmu-500

              - qcom,sa8775p-smmu-500

              - qcom,sc7280-smmu-500

              - qcom,sc8180x-smmu-500
@@ -552,7 +555,9 @@ allOf: 
              - cavium,smmu-v2

              - marvell,ap806-smmu-500

              - nvidia,smmu-500

              - qcom,qcs8300-smmu-500

              - qcom,qdu1000-smmu-500

              - qcom,sa8255p-smmu-500

              - qcom,sc7180-smmu-500

              - qcom,sdm670-smmu-500

              - qcom,sdm845-smmu-500

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -22650,6 +22650,7 @@ M: Thierry Reding <thierry.reding@gmail.com> 
R:	Krishna Reddy <vdumpa@nvidia.com>

L:	linux-tegra@vger.kernel.org

S:	Supported

F:	drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c

F:	drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c

F:	drivers/iommu/tegra*

























drivers/iommu/Kconfig



+11
−0






























Original line number
Diff line number
Diff line







@@ -424,6 +424,17 @@ config ARM_SMMU_V3_KUNIT_TEST







	  Enable this option to unit-test arm-smmu-v3 driver functions.



















	  If unsure, say N.



















config TEGRA241_CMDQV









	bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3"









	depends on ACPI









	help









	  Support for NVIDIA CMDQ-Virtualization extension for ARM SMMUv3. The









	  CMDQ-V extension is similar to v3.3 ECMDQ for multi command queues









	  support, except with virtualization capabilities.



















	  Say Y here if your system is NVIDIA Tegra241 (Grace) or it has the same









	  CMDQ-V extension.









endif



















config S390_IOMMU
































drivers/iommu/amd/amd_iommu.h



+2
−24






























Original line number
Diff line number
Diff line







@@ -43,9 +43,10 @@ int amd_iommu_enable_faulting(unsigned int cpu);







extern int amd_iommu_guest_ir;









extern enum io_pgtable_fmt amd_iommu_pgtable;









extern int amd_iommu_gpt_level;









extern unsigned long amd_iommu_pgsize_bitmap;



















/* Protection domain ops */









struct protection_domain *protection_domain_alloc(unsigned int type);









struct protection_domain *protection_domain_alloc(unsigned int type, int nid);









void protection_domain_free(struct protection_domain *domain);









struct iommu_domain *amd_iommu_domain_alloc_sva(struct device *dev,









						struct mm_struct *mm);








@@ -87,14 +88,10 @@ int amd_iommu_complete_ppr(struct device *dev, u32 pasid, int status, int tag);







void amd_iommu_flush_all_caches(struct amd_iommu *iommu);









void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);









void amd_iommu_domain_update(struct protection_domain *domain);









void amd_iommu_dev_update_dte(struct iommu_dev_data *dev_data, bool set);









void amd_iommu_domain_flush_complete(struct protection_domain *domain);









void amd_iommu_domain_flush_pages(struct protection_domain *domain,









				  u64 address, size_t size);









void amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data,









				     ioasid_t pasid, u64 address, size_t size);









void amd_iommu_dev_flush_pasid_all(struct iommu_dev_data *dev_data,









				   ioasid_t pasid);



















#ifdef CONFIG_IRQ_REMAP









int amd_iommu_create_irq_domain(struct amd_iommu *iommu);








@@ -121,11 +118,6 @@ static inline bool check_feature2(u64 mask)







	return (amd_iommu_efr2 & mask);









}



















static inline int check_feature_gpt_level(void)









{









	return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK);









}



















static inline bool amd_iommu_gt_ppr_supported(void)









{









	return (check_feature(FEATURE_GT) &&








@@ -143,19 +135,6 @@ static inline void *iommu_phys_to_virt(unsigned long paddr)







	return phys_to_virt(__sme_clr(paddr));









}



















static inline









void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)









{









	domain->iop.root = (u64 *)(root & PAGE_MASK);









	domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */









}



















static inline









void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)









{









	amd_iommu_domain_set_pt_root(domain, 0);









}



















static inline int get_pci_sbdf_id(struct pci_dev *pdev)









{









	int seg = pci_domain_nr(pdev->bus);








@@ -185,7 +164,6 @@ static inline struct protection_domain *to_pdomain(struct iommu_domain *dom)







}



















bool translation_pre_enabled(struct amd_iommu *iommu);









bool amd_iommu_is_attach_deferred(struct device *dev);









int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line);



















#ifdef CONFIG_DMI